drivers/pinctrl/intel/pinctrl-jasperlake.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/intel/pinctrl-jasperlake.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/intel/pinctrl-jasperlake.c
Extension
.c
Size
10540 bytes
Lines
336
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Jasper Lake PCH pinctrl/GPIO driver
 *
 * Copyright (C) 2020 Intel Corporation
 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 */

#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>

#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-intel.h"

#define JSL_PAD_OWN	0x020
#define JSL_PADCFGLOCK	0x080
#define JSL_HOSTSW_OWN	0x0c0
#define JSL_GPI_IS	0x100
#define JSL_GPI_IE	0x120

#define JSL_COMMUNITY(b, s, e, g)			\
	INTEL_COMMUNITY_GPPS(b, s, e, g, JSL)

/* Jasper Lake */
static const struct pinctrl_pin_desc jsl_pins[] = {
	/* GPP_F */
	PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"),
	PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"),
	PINCTRL_PIN(2, "EMMC_HIP_MON"),
	PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"),
	PINCTRL_PIN(4, "CNV_RF_RESET_B"),
	PINCTRL_PIN(5, "MODEM_CLKREQ"),
	PINCTRL_PIN(6, "CNV_PA_BLANKING"),
	PINCTRL_PIN(7, "EMMC_CMD"),
	PINCTRL_PIN(8, "EMMC_DATA0"),
	PINCTRL_PIN(9, "EMMC_DATA1"),
	PINCTRL_PIN(10, "EMMC_DATA2"),
	PINCTRL_PIN(11, "EMMC_DATA3"),
	PINCTRL_PIN(12, "EMMC_DATA4"),
	PINCTRL_PIN(13, "EMMC_DATA5"),
	PINCTRL_PIN(14, "EMMC_DATA6"),
	PINCTRL_PIN(15, "EMMC_DATA7"),
	PINCTRL_PIN(16, "EMMC_RCLK"),
	PINCTRL_PIN(17, "EMMC_CLK"),
	PINCTRL_PIN(18, "EMMC_RESETB"),
	PINCTRL_PIN(19, "A4WP_PRESENT"),
	/* SPI */
	PINCTRL_PIN(20, "SPI0_IO_2"),
	PINCTRL_PIN(21, "SPI0_IO_3"),
	PINCTRL_PIN(22, "SPI0_MOSI_IO_0"),
	PINCTRL_PIN(23, "SPI0_MISO_IO_1"),
	PINCTRL_PIN(24, "SPI0_TPM_CSB"),
	PINCTRL_PIN(25, "SPI0_FLASH_0_CSB"),
	PINCTRL_PIN(26, "SPI0_FLASH_1_CSB"),
	PINCTRL_PIN(27, "SPI0_CLK"),
	PINCTRL_PIN(28, "SPI0_CLK_LOOPBK"),
	/* GPP_B */
	PINCTRL_PIN(29, "CORE_VID_0"),
	PINCTRL_PIN(30, "CORE_VID_1"),
	PINCTRL_PIN(31, "VRALERTB"),
	PINCTRL_PIN(32, "CPU_GP_2"),
	PINCTRL_PIN(33, "CPU_GP_3"),
	PINCTRL_PIN(34, "SRCCLKREQB_0"),
	PINCTRL_PIN(35, "SRCCLKREQB_1"),
	PINCTRL_PIN(36, "SRCCLKREQB_2"),
	PINCTRL_PIN(37, "SRCCLKREQB_3"),
	PINCTRL_PIN(38, "SRCCLKREQB_4"),
	PINCTRL_PIN(39, "SRCCLKREQB_5"),
	PINCTRL_PIN(40, "PMCALERTB"),
	PINCTRL_PIN(41, "SLP_S0B"),
	PINCTRL_PIN(42, "PLTRSTB"),
	PINCTRL_PIN(43, "SPKR"),
	PINCTRL_PIN(44, "GSPI0_CS0B"),
	PINCTRL_PIN(45, "GSPI0_CLK"),
	PINCTRL_PIN(46, "GSPI0_MISO"),
	PINCTRL_PIN(47, "GSPI0_MOSI"),
	PINCTRL_PIN(48, "GSPI1_CS0B"),
	PINCTRL_PIN(49, "GSPI1_CLK"),
	PINCTRL_PIN(50, "GSPI1_MISO"),
	PINCTRL_PIN(51, "GSPI1_MOSI"),
	PINCTRL_PIN(52, "DDSP_HPD_A"),
	PINCTRL_PIN(53, "GSPI0_CLK_LOOPBK"),
	PINCTRL_PIN(54, "GSPI1_CLK_LOOPBK"),
	/* GPP_A */
	PINCTRL_PIN(55, "ESPI_IO_0"),
	PINCTRL_PIN(56, "ESPI_IO_1"),
	PINCTRL_PIN(57, "ESPI_IO_2"),

Annotation

Implementation Notes