drivers/pinctrl/intel/pinctrl-tigerlake.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/intel/pinctrl-tigerlake.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/intel/pinctrl-tigerlake.c
Extension
.c
Size
24119 bytes
Lines
754
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Tiger Lake PCH pinctrl/GPIO driver
 *
 * Copyright (C) 2019-2020 Intel Corporation
 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *          Mika Westerberg <mika.westerberg@linux.intel.com>
 */

#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>

#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-intel.h"

#define TGL_LP_PAD_OWN		0x020
#define TGL_LP_PADCFGLOCK	0x080
#define TGL_LP_HOSTSW_OWN	0x0b0
#define TGL_LP_GPI_IS		0x100
#define TGL_LP_GPI_IE		0x120

#define TGL_H_PAD_OWN		0x020
#define TGL_H_PADCFGLOCK	0x090
#define TGL_H_HOSTSW_OWN	0x0c0
#define TGL_H_GPI_IS		0x100
#define TGL_H_GPI_IE		0x120

#define TGL_LP_COMMUNITY(b, s, e, g)			\
	INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP)

#define TGL_H_COMMUNITY(b, s, e, g)			\
	INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_H)

/* Tiger Lake-LP */
static const struct pinctrl_pin_desc tgllp_pins[] = {
	/* GPP_B */
	PINCTRL_PIN(0, "CORE_VID_0"),
	PINCTRL_PIN(1, "CORE_VID_1"),
	PINCTRL_PIN(2, "VRALERTB"),
	PINCTRL_PIN(3, "CPU_GP_2"),
	PINCTRL_PIN(4, "CPU_GP_3"),
	PINCTRL_PIN(5, "ISH_I2C0_SDA"),
	PINCTRL_PIN(6, "ISH_I2C0_SCL"),
	PINCTRL_PIN(7, "ISH_I2C1_SDA"),
	PINCTRL_PIN(8, "ISH_I2C1_SCL"),
	PINCTRL_PIN(9, "I2C5_SDA"),
	PINCTRL_PIN(10, "I2C5_SCL"),
	PINCTRL_PIN(11, "PMCALERTB"),
	PINCTRL_PIN(12, "SLP_S0B"),
	PINCTRL_PIN(13, "PLTRSTB"),
	PINCTRL_PIN(14, "SPKR"),
	PINCTRL_PIN(15, "GSPI0_CS0B"),
	PINCTRL_PIN(16, "GSPI0_CLK"),
	PINCTRL_PIN(17, "GSPI0_MISO"),
	PINCTRL_PIN(18, "GSPI0_MOSI"),
	PINCTRL_PIN(19, "GSPI1_CS0B"),
	PINCTRL_PIN(20, "GSPI1_CLK"),
	PINCTRL_PIN(21, "GSPI1_MISO"),
	PINCTRL_PIN(22, "GSPI1_MOSI"),
	PINCTRL_PIN(23, "SML1ALERTB"),
	PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
	PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
	/* GPP_T */
	PINCTRL_PIN(26, "I2C6_SDA"),
	PINCTRL_PIN(27, "I2C6_SCL"),
	PINCTRL_PIN(28, "I2C7_SDA"),
	PINCTRL_PIN(29, "I2C7_SCL"),
	PINCTRL_PIN(30, "UART4_RXD"),
	PINCTRL_PIN(31, "UART4_TXD"),
	PINCTRL_PIN(32, "UART4_RTSB"),
	PINCTRL_PIN(33, "UART4_CTSB"),
	PINCTRL_PIN(34, "UART5_RXD"),
	PINCTRL_PIN(35, "UART5_TXD"),
	PINCTRL_PIN(36, "UART5_RTSB"),
	PINCTRL_PIN(37, "UART5_CTSB"),
	PINCTRL_PIN(38, "UART6_RXD"),
	PINCTRL_PIN(39, "UART6_TXD"),
	PINCTRL_PIN(40, "UART6_RTSB"),
	PINCTRL_PIN(41, "UART6_CTSB"),
	/* GPP_A */
	PINCTRL_PIN(42, "ESPI_IO_0"),
	PINCTRL_PIN(43, "ESPI_IO_1"),
	PINCTRL_PIN(44, "ESPI_IO_2"),
	PINCTRL_PIN(45, "ESPI_IO_3"),
	PINCTRL_PIN(46, "ESPI_CSB"),
	PINCTRL_PIN(47, "ESPI_CLK"),
	PINCTRL_PIN(48, "ESPI_RESETB"),

Annotation

Implementation Notes