drivers/pinctrl/mediatek/pinctrl-mt8135.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/mediatek/pinctrl-mt8135.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/mediatek/pinctrl-mt8135.c
Extension
.c
Size
11305 bytes
Lines
339
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mtk_spec_pull_set {
	unsigned char pin;
	unsigned char pupd_bit;
	unsigned short pupd_offset;
	unsigned short r0_offset;
	unsigned short r1_offset;
	unsigned char r0_bit;
	unsigned char r1_bit;
};

#define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \
	_r0_bit, _r1_offset, _r1_bit)	\
	{	\
		.pin = _pin,	\
		.pupd_offset = _pupd_offset,	\
		.pupd_bit = _pupd_bit,	\
		.r0_offset = _r0_offset, \
		.r0_bit = _r0_bit, \
		.r1_offset = _r1_offset, \
		.r1_bit = _r1_bit, \
	}

static const struct mtk_drv_group_desc mt8135_drv_grp[] =  {
	/* E8E4E2 2/4/6/8/10/12/14/16 */
	MTK_DRV_GRP(2, 16, 0, 2, 2),
	/* E8E4  4/8/12/16 */
	MTK_DRV_GRP(4, 16, 1, 2, 4),
	/* E4E2  2/4/6/8 */
	MTK_DRV_GRP(2, 8, 0, 1, 2),
	/* E16E8E4 4/8/12/16/20/24/28/32 */
	MTK_DRV_GRP(4, 32, 0, 2, 4)
};

static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {
	MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
	MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
	MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
	MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
	MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
	MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
	MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
	MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
	MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
	MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),

	MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
	MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
	MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
	MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
	MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
	MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
	MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
	MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
	MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
	MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
	MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
	MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
	MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
	MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
	MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
	MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
	MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
	MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
	MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
	MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
	MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
	MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
	MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
	MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
	MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
	MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
	MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
	MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),

	MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
	MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
	MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
	MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
	MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
	MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
	MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
	MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),

	MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
	MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
	MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
	MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
	MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
	MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
	MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),

Annotation

Implementation Notes