drivers/pinctrl/nuvoton/pinctrl-ma35d1.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/nuvoton/pinctrl-ma35d1.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/nuvoton/pinctrl-ma35d1.c
Extension
.c
Size
54406 bytes
Lines
1851
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2024 Nuvoton Technology Corp.
 *
 * Author: Shan-Chun Hung <schung@nuvoton.com>
 * *       Jacky Huang <ychuang3@nuvoton.com>
 */
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>

#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-ma35.h"

static const struct pinctrl_pin_desc ma35d1_pins[] = {
	MA35_PIN(0, PA0, 0x80, 0x0,
		MA35_MUX(0x0, "GPA0"),
		MA35_MUX(0x2, "UART1_nCTS"),
		MA35_MUX(0x3, "UART16_RXD"),
		MA35_MUX(0x6, "NAND_DATA0"),
		MA35_MUX(0x7, "EBI_AD0"),
		MA35_MUX(0x9, "EBI_ADR0")),
	MA35_PIN(1, PA1, 0x80, 0x4,
		MA35_MUX(0x0, "GPA1"),
		MA35_MUX(0x2, "UART1_nRTS"),
		MA35_MUX(0x3, "UART16_TXD"),
		MA35_MUX(0x6, "NAND_DATA1"),
		MA35_MUX(0x7, "EBI_AD1"),
		MA35_MUX(0x9, "EBI_ADR1")),
	MA35_PIN(2, PA2, 0x80, 0x8,
		MA35_MUX(0x0, "GPA2"),
		MA35_MUX(0x2, "UART1_RXD"),
		MA35_MUX(0x6, "NAND_DATA2"),
		MA35_MUX(0x7, "EBI_AD2"),
		MA35_MUX(0x9, "EBI_ADR2")),
	MA35_PIN(3, PA3, 0x80, 0xc,
		MA35_MUX(0x0, "GPA3"),
		MA35_MUX(0x2, "UART1_TXD"),
		MA35_MUX(0x6, "NAND_DATA3"),
		MA35_MUX(0x7, "EBI_AD3"),
		MA35_MUX(0x9, "EBI_ADR3")),
	MA35_PIN(4, PA4, 0x80, 0x10,
		MA35_MUX(0x0, "GPA4"),
		MA35_MUX(0x2, "UART3_nCTS"),
		MA35_MUX(0x3, "UART2_RXD"),
		MA35_MUX(0x6, "NAND_DATA4"),
		MA35_MUX(0x7, "EBI_AD4"),
		MA35_MUX(0x9, "EBI_ADR4")),
	MA35_PIN(5, PA5, 0x80, 0x14,
		MA35_MUX(0x0, "GPA5"),
		MA35_MUX(0x2, "UART3_nRTS"),
		MA35_MUX(0x3, "UART2_TXD"),
		MA35_MUX(0x6, "NAND_DATA5"),
		MA35_MUX(0x7, "EBI_AD5"),
		MA35_MUX(0x9, "EBI_ADR5")),
	MA35_PIN(6, PA6, 0x80, 0x18,
		MA35_MUX(0x0, "GPA6"),
		MA35_MUX(0x2, "UART3_RXD"),
		MA35_MUX(0x6, "NAND_DATA6"),
		MA35_MUX(0x7, "EBI_AD6"),
		MA35_MUX(0x9, "EBI_ADR6")),
	MA35_PIN(7, PA7, 0x80, 0x1c,
		MA35_MUX(0x0, "GPA7"),
		MA35_MUX(0x2, "UART3_TXD"),
		MA35_MUX(0x6, "NAND_DATA7"),
		MA35_MUX(0x7, "EBI_AD7"),
		MA35_MUX(0x9, "EBI_ADR7")),
	MA35_PIN(8, PA8, 0x84, 0x0,
		MA35_MUX(0x0, "GPA8"),
		MA35_MUX(0x2, "UART5_nCTS"),
		MA35_MUX(0x3, "UART4_RXD"),
		MA35_MUX(0x6, "NAND_RDY0"),
		MA35_MUX(0x7, "EBI_AD8"),
		MA35_MUX(0x9, "EBI_ADR8")),
	MA35_PIN(9, PA9, 0x84, 0x4,
		MA35_MUX(0x0, "GPA9"),
		MA35_MUX(0x2, "UART5_nRTS"),
		MA35_MUX(0x3, "UART4_TXD"),
		MA35_MUX(0x6, "NAND_nRE"),
		MA35_MUX(0x7, "EBI_AD9"),
		MA35_MUX(0x9, "EBI_ADR9")),
	MA35_PIN(10, PA10, 0x84, 0x8,
		MA35_MUX(0x0, "GPA10"),
		MA35_MUX(0x2, "UART5_RXD"),
		MA35_MUX(0x6, "NAND_nWE"),
		MA35_MUX(0x7, "EBI_AD10"),

Annotation

Implementation Notes