drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
Extension
.c
Size
95610 bytes
Lines
2475
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct debounce_time {
	bool	set_val[NPCM8XX_DEBOUNCE_MAX];
	u32	nanosec_val[NPCM8XX_DEBOUNCE_MAX];
};

struct npcm8xx_gpio {
	struct gpio_generic_chip chip;
	void __iomem		*base;
	struct debounce_time	debounce;
	int			irqbase;
	int			irq;
	struct irq_chip		irq_chip;
	u32			pinctrl_id;
	int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
	int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
				int value);
	int (*request)(struct gpio_chip *chip, unsigned int offset);
	void (*free)(struct gpio_chip *chip, unsigned int offset);
};

struct npcm8xx_pinctrl {
	struct pinctrl_dev	*pctldev;
	struct device		*dev;
	struct npcm8xx_gpio	gpio_bank[NPCM8XX_GPIO_BANK_NUM];
	struct irq_domain	*domain;
	struct regmap		*gcr_regmap;
	void __iomem		*regs;
	u32			bank_num;
};

/* GPIO handling in the pinctrl driver */
static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg,
			  unsigned int pinmask)
{
	guard(gpio_generic_lock_irqsave)(chip);

	iowrite32(ioread32(reg) | pinmask, reg);
}

static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg,
			  unsigned int pinmask)
{
	guard(gpio_generic_lock_irqsave)(chip);

	iowrite32(ioread32(reg) & ~pinmask, reg);
}

static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);

	seq_printf(s, "DIN :%.8x DOUT:%.8x IE  :%.8x OE	 :%.8x\n",
		   ioread32(bank->base + NPCM8XX_GP_N_DIN),
		   ioread32(bank->base + NPCM8XX_GP_N_DOUT),
		   ioread32(bank->base + NPCM8XX_GP_N_IEM),
		   ioread32(bank->base + NPCM8XX_GP_N_OE));
	seq_printf(s, "PU  :%.8x PD  :%.8x DB  :%.8x POL :%.8x\n",
		   ioread32(bank->base + NPCM8XX_GP_N_PU),
		   ioread32(bank->base + NPCM8XX_GP_N_PD),
		   ioread32(bank->base + NPCM8XX_GP_N_DBNC),
		   ioread32(bank->base + NPCM8XX_GP_N_POL));
	seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
		   ioread32(bank->base + NPCM8XX_GP_N_EVTYP),
		   ioread32(bank->base + NPCM8XX_GP_N_EVBE),
		   ioread32(bank->base + NPCM8XX_GP_N_EVEN),
		   ioread32(bank->base + NPCM8XX_GP_N_EVST));
	seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
		   ioread32(bank->base + NPCM8XX_GP_N_OTYP),
		   ioread32(bank->base + NPCM8XX_GP_N_OSRC),
		   ioread32(bank->base + NPCM8XX_GP_N_ODSC));
	seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
		   ioread32(bank->base + NPCM8XX_GP_N_OBL0),
		   ioread32(bank->base + NPCM8XX_GP_N_OBL1),
		   ioread32(bank->base + NPCM8XX_GP_N_OBL2),
		   ioread32(bank->base + NPCM8XX_GP_N_OBL3));
	seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
		   ioread32(bank->base + NPCM8XX_GP_N_SPLCK),
		   ioread32(bank->base + NPCM8XX_GP_N_MPLCK));
}

static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
{
	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
	int ret;

	ret = pinctrl_gpio_direction_input(chip, offset);
	if (ret)
		return ret;

	return bank->direction_input(chip, offset);

Annotation

Implementation Notes