drivers/pinctrl/pinctrl-ep93xx.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/pinctrl-ep93xx.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/pinctrl-ep93xx.c
Extension
.c
Size
47491 bytes
Lines
1435
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ep93xx_pmx {
	struct device *dev;
	struct pinctrl_dev *pctl;
	struct ep93xx_regmap_adev *aux_dev;
	struct regmap *map;
	enum ep93xx_pinctrl_model model;
};

static void ep93xx_pinctrl_update_bits(struct ep93xx_pmx *pmx, unsigned int reg,
				       unsigned int mask, unsigned int val)
{
	struct ep93xx_regmap_adev *aux = pmx->aux_dev;

	aux->update_bits(aux->map, aux->lock, reg, mask, val);
}

struct ep93xx_pin_group {
	struct pingroup grp;
	u32 mask;
	u32 value;
};

#define PMX_GROUP(_name, _pins, _mask, _value)					\
	{									\
		.grp = PINCTRL_PINGROUP(_name, _pins, ARRAY_SIZE(_pins)),	\
		.mask = _mask,							\
		.value = _value,						\
	}

#define EP93XX_SYSCON_DEVCFG		0x80

/*
 * There are several system configuration options selectable by the DeviceCfg and SysCfg
 * registers. These registers provide the selection of several pin multiplexing options and also
 * provide software access to the system reset configuration options. Please refer to the
 * descriptions of the registers, “DeviceCfg” on page 5-25 and “SysCfg” on page 5-34, for a
 * detailed explanation.
 */
#define EP93XX_SYSCON_DEVCFG_D1ONG	BIT(30)
#define EP93XX_SYSCON_DEVCFG_D0ONG	BIT(29)
#define EP93XX_SYSCON_DEVCFG_IONU2	BIT(28)
#define EP93XX_SYSCON_DEVCFG_GONK	BIT(27)
#define EP93XX_SYSCON_DEVCFG_TONG	BIT(26)
#define EP93XX_SYSCON_DEVCFG_MONG	BIT(25)
#define EP93XX_SYSCON_DEVCFG_A2ONG	BIT(22)
#define EP93XX_SYSCON_DEVCFG_A1ONG	BIT(21)
#define EP93XX_SYSCON_DEVCFG_HONIDE	BIT(11)
#define EP93XX_SYSCON_DEVCFG_GONIDE	BIT(10)
#define EP93XX_SYSCON_DEVCFG_PONG	BIT(9)
#define EP93XX_SYSCON_DEVCFG_EONIDE	BIT(8)
#define EP93XX_SYSCON_DEVCFG_I2SONSSP	BIT(7)
#define EP93XX_SYSCON_DEVCFG_I2SONAC97	BIT(6)
#define EP93XX_SYSCON_DEVCFG_RASONP3	BIT(4)

#define PADS_MASK		(GENMASK(30, 25) | BIT(22) | BIT(21) | GENMASK(11, 6) | BIT(4))
#define PADS_MAXBIT		30

/* Ordered by bit index */
static const char * const ep93xx_padgroups[] = {
	NULL, NULL, NULL, NULL,
	"RasOnP3",
	NULL,
	"I2SonAC97",
	"I2SonSSP",
	"EonIDE",
	"PonG",
	"GonIDE",
	"HonIDE",
	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
	"A1onG",
	"A2onG",
	NULL, NULL,
	"MonG",
	"TonG",
	"GonK",
	"IonU2",
	"D0onG",
	"D1onG",
};

/* ep9301, ep9302 */
static const struct pinctrl_pin_desc ep9301_pins[] = {
	PINCTRL_PIN(1, "CSn[7]"),
	PINCTRL_PIN(2, "CSn[6]"),
	PINCTRL_PIN(3, "CSn[3]"),
	PINCTRL_PIN(4, "CSn[2]"),
	PINCTRL_PIN(5, "CSn[1]"),
	PINCTRL_PIN(6, "AD[25]"),
	PINCTRL_PIN(7, "vdd_ring"),
	PINCTRL_PIN(8, "gnd_ring"),

Annotation

Implementation Notes