drivers/pinctrl/pinctrl-equilibrium.c
Source file repositories/reference/linux-study-clean/drivers/pinctrl/pinctrl-equilibrium.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pinctrl/pinctrl-equilibrium.c- Extension
.c- Size
- 24231 bytes
- Lines
- 972
- Domain
- Driver Families
- Bucket
- drivers/pinctrl
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/gpio/driver.hlinux/gpio/generic.hlinux/module.hlinux/of.hlinux/of_address.hlinux/of_irq.hlinux/pinctrl/pinctrl.hlinux/pinctrl/pinconf.hlinux/pinctrl/pinconf-generic.hlinux/pinctrl/pinmux.hlinux/platform_device.hlinux/property.hcore.hpinconf.hpinmux.hpinctrl-equilibrium.h
Detected Declarations
function eqbr_irq_maskfunction eqbr_irq_unmaskfunction eqbr_irq_ackfunction eqbr_irq_mask_ackfunction eqbr_cfg_bitfunction eqbr_irq_type_cfgfunction eqbr_irq_set_typefunction eqbr_irq_handlerfunction gpiochip_setupfunction gpiolib_regfunction eqbr_set_pin_muxfunction eqbr_pinmux_set_muxfunction eqbr_pinmux_gpio_requestfunction get_drv_curfunction eqbr_pinconf_getfunction eqbr_pinconf_setfunction eqbr_pinconf_group_getfunction eqbr_pinconf_group_setfunction is_func_existfunction funcs_utilsfunction eqbr_build_functionsfunction eqbr_build_groupsfunction for_each_child_of_node_scopedfunction pinctrl_regfunction pinbank_initfunction pinbank_probefunction eqbr_pinctrl_probe
Annotated Snippet
if (of_address_to_resource(np, 0, &res)) {
dev_err(dev, "Failed to get GPIO register address\n");
return -ENXIO;
}
gctrl->membase = devm_ioremap_resource(dev, &res);
if (IS_ERR(gctrl->membase))
return PTR_ERR(gctrl->membase);
gctrl->virq = irq_of_parse_and_map(np, 0);
if (!gctrl->virq) {
dev_err(dev, "%s: failed to parse and map irq\n",
gctrl->name);
return -ENXIO;
}
raw_spin_lock_init(&gctrl->lock);
config = (struct gpio_generic_chip_config) {
.dev = dev,
.sz = gctrl->bank->nr_pins / 8,
.dat = gctrl->membase + GPIO_IN,
.set = gctrl->membase + GPIO_OUTSET,
.clr = gctrl->membase + GPIO_OUTCLR,
.dirout = gctrl->membase + GPIO_DIR,
};
ret = gpio_generic_chip_init(&gctrl->chip, &config);
if (ret) {
dev_err(dev, "unable to init generic GPIO\n");
return ret;
}
ret = gpiochip_setup(dev, gctrl);
if (ret)
return ret;
ret = devm_gpiochip_add_data(dev, &gctrl->chip.gc, gctrl);
if (ret)
return ret;
}
return 0;
}
static inline struct eqbr_pin_bank
*find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin)
{
struct eqbr_pin_bank *bank;
int i;
for (i = 0; i < pctl->nr_banks; i++) {
bank = &pctl->pin_banks[i];
if (pin >= bank->pin_base &&
(pin - bank->pin_base) < bank->nr_pins)
return bank;
}
return NULL;
}
static const struct pinctrl_ops eqbr_pctl_ops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinconf_generic_dt_free_map,
};
static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl,
unsigned int pmx, unsigned int pin)
{
struct eqbr_pin_bank *bank;
unsigned long flags;
unsigned int offset;
void __iomem *mem;
bank = find_pinbank_via_pin(pctl, pin);
if (!bank) {
dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
return -ENODEV;
}
mem = bank->membase;
offset = pin - bank->pin_base;
if (!(bank->aval_pinmap & BIT(offset))) {
dev_err(pctl->dev,
"PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
pin, bank->pin_base, bank->aval_pinmap);
return -ENODEV;
}
Annotation
- Immediate include surface: `linux/gpio/driver.h`, `linux/gpio/generic.h`, `linux/module.h`, `linux/of.h`, `linux/of_address.h`, `linux/of_irq.h`, `linux/pinctrl/pinctrl.h`, `linux/pinctrl/pinconf.h`.
- Detected declarations: `function eqbr_irq_mask`, `function eqbr_irq_unmask`, `function eqbr_irq_ack`, `function eqbr_irq_mask_ack`, `function eqbr_cfg_bit`, `function eqbr_irq_type_cfg`, `function eqbr_irq_set_type`, `function eqbr_irq_handler`, `function gpiochip_setup`, `function gpiolib_reg`.
- Atlas domain: Driver Families / drivers/pinctrl.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.