drivers/pinctrl/pinctrl-eyeq5.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/pinctrl-eyeq5.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/pinctrl-eyeq5.c
Extension
.c
Size
25426 bytes
Lines
755
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct eq5p_bank {
	const unsigned int npins;
	const unsigned int regs[EQ5P_REG_COUNT];
};

struct eq5p_match_data {
	const unsigned int npins;
	const unsigned int nfunctions;
	const unsigned int nbanks;
	const struct pinctrl_pin_desc *pins;
	const struct pinfunction *functions;
	const struct eq5p_bank *banks;
};

struct eq5p_pinctrl {
	struct pinctrl_desc		desc;
	void __iomem			*base;
	const struct eq5p_match_data	*data;
};

/*
 * Drive strength; two bits per pin.
 */
#define EQ5P_DS_MASK	GENMASK(1, 0)

/*
 * The GPIO function is always the first function
 */
#define EQ5P_GPIO_FUNC_SELECTOR 0

/* Helper to declare pinfunction */
#define EQ5P_PINFUNCTION(func, groups) PINCTRL_PINFUNCTION(func, groups, ARRAY_SIZE(groups))

/*
 * Comments to the right of each pin are the "signal name" in the datasheet.
 */
static const struct pinctrl_pin_desc eq5p_eyeq5_pins[] = {
	/* Bank A */
	PINCTRL_PIN(0,  "PA0"),  /* A0_TIMER0_CK */
	PINCTRL_PIN(1,  "PA1"),  /* A1_TIMER0_EOC */
	PINCTRL_PIN(2,  "PA2"),  /* A2_TIMER1_CK */
	PINCTRL_PIN(3,  "PA3"),  /* A3_TIMER1_EOC */
	PINCTRL_PIN(4,  "PA4"),  /* A4_TIMER2_CK */
	PINCTRL_PIN(5,  "PA5"),  /* A5_TIMER2_EOC */
	PINCTRL_PIN(6,  "PA6"),  /* A6_TIMER5_EXT_INCAP1 */
	PINCTRL_PIN(7,  "PA7"),  /* A7_TIMER5_EXT_INCAP2 */
	PINCTRL_PIN(8,  "PA8"),  /* A8_TIMER5_EXT_OUTCMP1 */
	PINCTRL_PIN(9,  "PA9"),  /* A9_TIMER5_EXT_OUTCMP2 */
	PINCTRL_PIN(10, "PA10"), /* A10_UART_0_TX */
	PINCTRL_PIN(11, "PA11"), /* A11_UART_0_RX */
	PINCTRL_PIN(12, "PA12"), /* A12_UART_1_TX */
	PINCTRL_PIN(13, "PA13"), /* A13_UART_1_RX */
	PINCTRL_PIN(14, "PA14"), /* A14_CAN_0_TX */
	PINCTRL_PIN(15, "PA15"), /* A15_CAN_0_RX */
	PINCTRL_PIN(16, "PA16"), /* A16_CAN_1_TX */
	PINCTRL_PIN(17, "PA17"), /* A17_CAN_1_RX */
	PINCTRL_PIN(18, "PA18"), /* A18_SPI_0_DO */
	PINCTRL_PIN(19, "PA19"), /* A19_SPI_0_DI */
	PINCTRL_PIN(20, "PA20"), /* A20_SPI_0_CK */
	PINCTRL_PIN(21, "PA21"), /* A21_SPI_0_CS0 */
	PINCTRL_PIN(22, "PA22"), /* A22_SPI_0_CS1 */
	PINCTRL_PIN(23, "PA23"), /* A23_SPI_1_DO */
	PINCTRL_PIN(24, "PA24"), /* A24_SPI_1_DI */
	PINCTRL_PIN(25, "PA25"), /* A25_SPI_1_CK */
	PINCTRL_PIN(26, "PA26"), /* A26_SPI_1_CS0 */
	PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */
	PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */

#define EQ5P_EYEQ5_PIN_OFFSET_BANK_B	29

	/* Bank B */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 0,  "PB0"),  /* B0_TIMER3_CK */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 1,  "PB1"),  /* B1_TIMER3_EOC */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 2,  "PB2"),  /* B2_TIMER4_CK */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 3,  "PB3"),  /* B3_TIMER4_EOC */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 4,  "PB4"),  /* B4_TIMER6_EXT_INCAP1 */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 5,  "PB5"),  /* B5_TIMER6_EXT_INCAP2 */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 6,  "PB6"),  /* B6_TIMER6_EXT_OUTCMP1 */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 7,  "PB7"),  /* B7_TIMER6_EXT_OUTCMP2 */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 8,  "PB8"),  /* B8_UART_2_TX */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 9,  "PB9"),  /* B9_UART_2_RX */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */
	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */

Annotation

Implementation Notes