drivers/pinctrl/pinctrl-gemini.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/pinctrl-gemini.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/pinctrl-gemini.c
Extension
.c
Size
78973 bytes
Lines
2629
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct gemini_pin_conf {
	unsigned int pin;
	u32 reg;
	u32 mask;
};

/**
 * struct gemini_pmx - state holder for the gemini pin controller
 * @dev: a pointer back to containing device
 * @virtbase: the offset to the controller in virtual memory
 * @map: regmap to access registers
 * @is_3512: whether the SoC/package is the 3512 variant
 * @is_3516: whether the SoC/package is the 3516 variant
 * @flash_pin: whether the flash pin (extended pins for parallel
 * flash) is set
 * @confs: pin config information
 * @nconfs: number of pin config information items
 */
struct gemini_pmx {
	struct device *dev;
	struct pinctrl_dev *pctl;
	struct regmap *map;
	bool is_3512;
	bool is_3516;
	bool flash_pin;
	const struct gemini_pin_conf *confs;
	unsigned int nconfs;
};

/**
 * struct gemini_pin_group - describes a Gemini pin group
 * @name: the name of this specific pin group
 * @pins: an array of discrete physical pins used in this group, taken
 *	from the driver-local pin enumeration space
 * @num_pins: the number of pins in this group array, i.e. the number of
 *	elements in .pins so we can iterate over that array
 * @mask: bits to clear to enable this when doing pin muxing
 * @value: bits to set to enable this when doing pin muxing
 * @driving_mask: bitmask for the IO Pad driving register for this
 *	group, if it supports altering the driving strength of
 *	its lines.
 */
struct gemini_pin_group {
	const char *name;
	const unsigned int *pins;
	const unsigned int num_pins;
	u32 mask;
	u32 value;
	u32 driving_mask;
};

/* Some straight-forward control registers */
#define GLOBAL_WORD_ID		0x00
#define GLOBAL_STATUS		0x04
#define GLOBAL_STATUS_FLPIN	BIT(20)
#define GLOBAL_IODRIVE		0x10
#define GLOBAL_GMAC_CTRL_SKEW	0x1c
#define GLOBAL_GMAC0_DATA_SKEW	0x20
#define GLOBAL_GMAC1_DATA_SKEW	0x24
/*
 * Global Miscellaneous Control Register
 * This register controls all Gemini pad/pin multiplexing
 *
 * It is a tricky register though:
 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
 *   be brought back online, so it means permanent disablement of the
 *   corresponding pads.
 * - For the bits named *_DISABLE, once you enable something, it cannot be
 *   DISABLED again. So you select a flash configuration once, and then
 *   you are stuck with it.
 */
#define GLOBAL_MISC_CTRL	0x30
#define GEMINI_GMAC_IOSEL_MASK	GENMASK(28, 27)
/* Not really used */
#define GEMINI_GMAC_IOSEL_GMAC0_GMII	BIT(28)
/* Activated with GMAC1 */
#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
/* This will be the default */
#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
#define TVC_CLK_PAD_ENABLE	BIT(20)
#define PCI_CLK_PAD_ENABLE	BIT(17)
#define LPC_CLK_PAD_ENABLE	BIT(16)
#define TVC_PADS_ENABLE		BIT(9)
#define SSP_PADS_ENABLE		BIT(8)
#define LCD_PADS_ENABLE		BIT(7)
#define LPC_PADS_ENABLE		BIT(6)
#define PCI_PADS_ENABLE		BIT(5)
#define IDE_PADS_ENABLE		BIT(4)
#define DRAM_PADS_POWERDOWN	BIT(3)
#define NAND_PADS_DISABLE	BIT(2)

Annotation

Implementation Notes