drivers/pinctrl/pinctrl-keembay.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/pinctrl-keembay.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/pinctrl-keembay.c
Extension
.c
Size
51834 bytes
Lines
1720
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct keembay_mux_desc {
	u8 mode;
	const char *name;
};

#define KEEMBAY_PIN_DESC(pin_number, pin_name, ...) {	\
	.number = pin_number,				\
	.name = pin_name,				\
	.drv_data = &(struct keembay_mux_desc[]) {	\
		    __VA_ARGS__, { } },			\
}							\

#define KEEMBAY_MUX(pin_mode, pin_function) {		\
	.mode = pin_mode,				\
	.name = pin_function,				\
}							\

/**
 * struct keembay_gpio_irq - Config of each GPIO Interrupt sources
 * @source: Interrupt source number (0 - 7)
 * @line: Actual Interrupt line number
 * @pins: Array of GPIO pins using this Interrupt line
 * @trigger: Interrupt trigger type for this line
 * @num_share: Number of pins currently using this Interrupt line
 */
struct keembay_gpio_irq {
	unsigned int source;
	unsigned int line;
	unsigned int pins[KEEMBAY_GPIO_MAX_PER_IRQ];
	unsigned int trigger;
	unsigned int num_share;
};

/**
 * struct keembay_pinctrl - Intel Keembay pinctrl structure
 * @pctrl: Pointer to the pin controller device
 * @base0: First register base address
 * @base1: Second register base address
 * @dev: Pointer to the device structure
 * @chip: GPIO chip used by this pin controller
 * @soc: Pin control configuration data based on SoC
 * @lock: Spinlock to protect various gpio config register access
 * @ngroups: Number of pin groups available
 * @nfuncs: Number of pin functions available
 * @npins: Number of GPIO pins available
 * @irq: Store Interrupt source
 * @max_gpios_level_type: Store max level trigger type
 * @max_gpios_edge_type: Store max edge trigger type
 */
struct keembay_pinctrl {
	struct pinctrl_dev *pctrl;
	void __iomem *base0;
	void __iomem *base1;
	struct device *dev;
	struct gpio_chip chip;
	const struct keembay_pin_soc *soc;
	raw_spinlock_t lock;
	unsigned int ngroups;
	unsigned int nfuncs;
	unsigned int npins;
	struct keembay_gpio_irq irq[KEEMBAY_GPIO_NUM_IRQ];
	int max_gpios_level_type;
	int max_gpios_edge_type;
};

/**
 * struct keembay_pin_soc - Pin control config data based on SoC
 * @pins: Pin description structure
 */
struct keembay_pin_soc {
	const struct pinctrl_pin_desc *pins;
};

struct keembay_pinfunction {
	struct pinfunction func;
	u8 mux_mode;
};

static const struct pinctrl_pin_desc keembay_pins[] = {
	KEEMBAY_PIN_DESC(0, "GPIO0",
			 KEEMBAY_MUX(0x0, "I2S0_M0"),
			 KEEMBAY_MUX(0x1, "SD0_M1"),
			 KEEMBAY_MUX(0x2, "SLVDS0_M2"),
			 KEEMBAY_MUX(0x3, "I2C0_M3"),
			 KEEMBAY_MUX(0x4, "CAM_M4"),
			 KEEMBAY_MUX(0x5, "ETH_M5"),
			 KEEMBAY_MUX(0x6, "LCD_M6"),
			 KEEMBAY_MUX(0x7, "GPIO_M7")),
	KEEMBAY_PIN_DESC(1, "GPIO1",
			 KEEMBAY_MUX(0x0, "I2S0_M0"),

Annotation

Implementation Notes