drivers/pinctrl/pinctrl-rp1.c
Source file repositories/reference/linux-study-clean/drivers/pinctrl/pinctrl-rp1.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pinctrl/pinctrl-rp1.c- Extension
.c- Size
- 52728 bytes
- Lines
- 1914
- Domain
- Driver Families
- Bucket
- drivers/pinctrl
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/gpio/driver.hlinux/of_irq.hlinux/pinctrl/pinconf.hlinux/pinctrl/pinmux.hlinux/platform_device.hlinux/seq_file.hlinux/regmap.hpinmux.hpinconf.hpinctrl-utils.h
Detected Declarations
struct rp1_pin_funcsstruct rp1_iobank_descstruct rp1_pin_infostruct rp1_pinctrlenum funcsfunction rp1_input_enablefunction rp1_output_enablefunction rp1_get_fselfunction rp1_set_fselfunction rp1_get_dirfunction rp1_set_dirfunction rp1_get_valuefunction rp1_set_valuefunction rp1_gpio_getfunction rp1_gpio_setfunction rp1_gpio_get_directionfunction rp1_gpio_direction_inputfunction rp1_gpio_direction_outputfunction rp1_gpio_set_configfunction rp1_gpio_irq_handlerfunction rp1_gpio_irq_configfunction rp1_gpio_irq_enablefunction rp1_gpio_irq_disablefunction rp1_irq_set_typefunction rp1_gpio_irq_set_typefunction rp1_gpio_irq_ackfunction rp1_gpio_irq_set_affinityfunction rp1_pctl_get_groups_countfunction rp1_get_fsel_funcfunction rp1_pctl_get_group_pinsfunction rp1_pctl_pin_dbg_showfunction rp1_pctl_dt_free_mapfunction rp1_pctl_legacy_map_funcfunction rp1_pctl_legacy_map_pullfunction rp1_pctl_dt_node_to_mapfunction rp1_pmx_freefunction rp1_pmx_get_functions_countfunction rp1_pmx_get_function_groupsfunction rp1_pmx_setfunction rp1_pmx_gpio_disable_freefunction rp1_pmx_gpio_set_directionfunction rp1_pull_config_setfunction rp1_pinconf_setfunction rp1_pinconf_getfunction rp1_pinconf_group_getfunction rp1_pinconf_group_setfunction rp1_gen_regfieldfunction rp1_pinctrl_probe
Annotated Snippet
struct rp1_pin_funcs {
u8 funcs[RP1_FSEL_COUNT];
};
struct rp1_iobank_desc {
int min_gpio;
int num_gpios;
int gpio_offset;
int inte_offset;
int ints_offset;
int rio_offset;
int pads_offset;
};
struct rp1_pin_info {
u8 num;
u8 bank;
u8 offset;
u8 fsel;
u8 irq_type;
struct regmap_field *gpio[ARRAY_SIZE(rp1_gpio_fields)];
struct regmap_field *rio[ARRAY_SIZE(rp1_rio_fields)];
struct regmap_field *inte[ARRAY_SIZE(rp1_inte_fields)];
struct regmap_field *pad[ARRAY_SIZE(rp1_pad_fields)];
};
struct rp1_pinctrl {
struct device *dev;
void __iomem *gpio_base;
void __iomem *rio_base;
void __iomem *pads_base;
int irq[RP1_NUM_BANKS];
struct rp1_pin_info pins[RP1_NUM_GPIOS];
struct pinctrl_dev *pctl_dev;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range gpio_range;
raw_spinlock_t irq_lock[RP1_NUM_BANKS];
};
/* pins are just named GPIO0..GPIO53 */
#define RP1_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
static struct pinctrl_pin_desc rp1_gpio_pins[] = {
RP1_GPIO_PIN(0),
RP1_GPIO_PIN(1),
RP1_GPIO_PIN(2),
RP1_GPIO_PIN(3),
RP1_GPIO_PIN(4),
RP1_GPIO_PIN(5),
RP1_GPIO_PIN(6),
RP1_GPIO_PIN(7),
RP1_GPIO_PIN(8),
RP1_GPIO_PIN(9),
RP1_GPIO_PIN(10),
RP1_GPIO_PIN(11),
RP1_GPIO_PIN(12),
RP1_GPIO_PIN(13),
RP1_GPIO_PIN(14),
RP1_GPIO_PIN(15),
RP1_GPIO_PIN(16),
RP1_GPIO_PIN(17),
RP1_GPIO_PIN(18),
RP1_GPIO_PIN(19),
RP1_GPIO_PIN(20),
RP1_GPIO_PIN(21),
RP1_GPIO_PIN(22),
RP1_GPIO_PIN(23),
RP1_GPIO_PIN(24),
RP1_GPIO_PIN(25),
RP1_GPIO_PIN(26),
RP1_GPIO_PIN(27),
RP1_GPIO_PIN(28),
RP1_GPIO_PIN(29),
RP1_GPIO_PIN(30),
RP1_GPIO_PIN(31),
RP1_GPIO_PIN(32),
RP1_GPIO_PIN(33),
RP1_GPIO_PIN(34),
RP1_GPIO_PIN(35),
RP1_GPIO_PIN(36),
RP1_GPIO_PIN(37),
RP1_GPIO_PIN(38),
RP1_GPIO_PIN(39),
RP1_GPIO_PIN(40),
RP1_GPIO_PIN(41),
RP1_GPIO_PIN(42),
RP1_GPIO_PIN(43),
RP1_GPIO_PIN(44),
Annotation
- Immediate include surface: `linux/gpio/driver.h`, `linux/of_irq.h`, `linux/pinctrl/pinconf.h`, `linux/pinctrl/pinmux.h`, `linux/platform_device.h`, `linux/seq_file.h`, `linux/regmap.h`, `pinmux.h`.
- Detected declarations: `struct rp1_pin_funcs`, `struct rp1_iobank_desc`, `struct rp1_pin_info`, `struct rp1_pinctrl`, `enum funcs`, `function rp1_input_enable`, `function rp1_output_enable`, `function rp1_get_fsel`, `function rp1_set_fsel`, `function rp1_get_dir`.
- Atlas domain: Driver Families / drivers/pinctrl.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.