drivers/pinctrl/pinctrl-single.c
Source file repositories/reference/linux-study-clean/drivers/pinctrl/pinctrl-single.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pinctrl/pinctrl-single.c- Extension
.c- Size
- 50340 bytes
- Lines
- 2007
- Domain
- Driver Families
- Bucket
- drivers/pinctrl
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/module.hlinux/io.hlinux/platform_device.hlinux/slab.hlinux/err.hlinux/list.hlinux/interrupt.hlinux/irqchip/chained_irq.hlinux/of.hlinux/of_irq.hlinux/seq_file.hlinux/pinctrl/pinconf-generic.hlinux/pinctrl/pinconf.hlinux/pinctrl/pinctrl.hlinux/pinctrl/pinmux.hlinux/platform_data/pinctrl-single.hcore.hdevicetree.hpinconf.hpinmux.h
Detected Declarations
struct pcs_func_valsstruct pcs_conf_valsstruct pcs_conf_typestruct pcs_functionstruct pcs_gpiofunc_rangestruct pcs_datastruct pcs_soc_datastruct pcs_devicestruct pcs_interruptfunction pcs_readbfunction pcs_readwfunction pcs_readlfunction pcs_writebfunction pcs_writewfunction pcs_writelfunction pcs_pin_reg_offset_getfunction pcs_pin_shift_reg_getfunction pcs_pin_dbg_showfunction pcs_dt_free_mapfunction pcs_get_functionfunction pcs_set_muxfunction pcs_request_gpiofunction list_for_each_safefunction pcs_pinconf_clear_biasfunction pcs_pinconf_bias_disablefunction pcs_pinconf_getfunction pcs_pinconf_setfunction pcs_pinconf_group_getfunction pcs_pinconf_group_setfunction pcs_pinconf_dbg_showfunction pcs_add_pinfunction pcs_allocate_pin_tablefunction pcs_add_functionfunction pcs_get_pin_by_offsetfunction pcs_config_matchfunction add_configfunction add_settingfunction pcs_add_conf2function pcs_add_conf4function pcs_parse_pinconffunction pcs_parse_one_pinctrl_entryfunction pcs_parse_bits_in_pinctrl_entryfunction pcs_dt_node_to_mapfunction pcs_irq_freefunction pcs_free_resourcesfunction pcs_add_gpio_funcfunction pcs_irq_setfunction pcs_irq_mask
Annotated Snippet
struct pcs_func_vals {
void __iomem *reg;
unsigned val;
unsigned mask;
};
/**
* struct pcs_conf_vals - pinconf parameter, pinconf register offset
* and value, enable, disable, mask
* @param: config parameter
* @val: user input bits in the pinconf register
* @enable: enable bits in the pinconf register
* @disable: disable bits in the pinconf register
* @mask: mask bits in the register value
*/
struct pcs_conf_vals {
enum pin_config_param param;
unsigned val;
unsigned enable;
unsigned disable;
unsigned mask;
};
/**
* struct pcs_conf_type - pinconf property name, pinconf param pair
* @name: property name in DTS file
* @param: config parameter
*/
struct pcs_conf_type {
const char *name;
enum pin_config_param param;
};
/**
* struct pcs_function - pinctrl function
* @name: pinctrl function name
* @vals: register and vals array
* @nvals: number of entries in vals array
* @conf: array of pin configurations
* @nconfs: number of pin configurations available
* @node: list node
*/
struct pcs_function {
const char *name;
struct pcs_func_vals *vals;
unsigned nvals;
struct pcs_conf_vals *conf;
int nconfs;
struct list_head node;
};
/**
* struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
* @offset: offset base of pins
* @npins: number pins with the same mux value of gpio function
* @gpiofunc: mux value of gpio function
* @node: list node
*/
struct pcs_gpiofunc_range {
unsigned offset;
unsigned npins;
unsigned gpiofunc;
struct list_head node;
};
/**
* struct pcs_data - wrapper for data needed by pinctrl framework
* @pa: pindesc array
* @cur: index to current element
*
* REVISIT: We should be able to drop this eventually by adding
* support for registering pins individually in the pinctrl
* framework for those drivers that don't need a static array.
*/
struct pcs_data {
struct pinctrl_pin_desc *pa;
int cur;
};
/**
* struct pcs_soc_data - SoC specific settings
* @flags: initial SoC specific PCS_FEAT_xxx values
* @irq: optional interrupt for the controller
* @irq_enable_mask: optional SoC specific interrupt enable mask
* @irq_status_mask: optional SoC specific interrupt status mask
* @rearm: optional SoC specific wake-up rearm function
*/
struct pcs_soc_data {
unsigned flags;
int irq;
Annotation
- Immediate include surface: `linux/init.h`, `linux/module.h`, `linux/io.h`, `linux/platform_device.h`, `linux/slab.h`, `linux/err.h`, `linux/list.h`, `linux/interrupt.h`.
- Detected declarations: `struct pcs_func_vals`, `struct pcs_conf_vals`, `struct pcs_conf_type`, `struct pcs_function`, `struct pcs_gpiofunc_range`, `struct pcs_data`, `struct pcs_soc_data`, `struct pcs_device`, `struct pcs_interrupt`, `function pcs_readb`.
- Atlas domain: Driver Families / drivers/pinctrl.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.