drivers/pinctrl/pinctrl-stmfx.c
Source file repositories/reference/linux-study-clean/drivers/pinctrl/pinctrl-stmfx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pinctrl/pinctrl-stmfx.c- Extension
.c- Size
- 23605 bytes
- Lines
- 868
- Domain
- Driver Families
- Bucket
- drivers/pinctrl
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/gpio/driver.hlinux/interrupt.hlinux/mfd/stmfx.hlinux/module.hlinux/platform_device.hlinux/seq_file.hlinux/string_choices.hlinux/pinctrl/pinconf.hlinux/pinctrl/pinmux.hcore.hpinctrl-utils.h
Detected Declarations
struct stmfx_pinctrlfunction stmfx_gpio_getfunction stmfx_gpio_setfunction stmfx_gpio_get_directionfunction stmfx_gpio_direction_inputfunction stmfx_gpio_direction_outputfunction stmfx_pinconf_get_pupdfunction stmfx_pinconf_set_pupdfunction stmfx_pinconf_get_typefunction stmfx_pinconf_set_typefunction stmfx_pinconf_getfunction stmfx_pinconf_setfunction stmfx_pinconf_dbg_showfunction stmfx_pinctrl_get_groups_countfunction stmfx_pinctrl_get_group_pinsfunction stmfx_pinctrl_irq_maskfunction stmfx_pinctrl_irq_unmaskfunction stmfx_pinctrl_irq_set_typefunction stmfx_pinctrl_irq_bus_lockfunction stmfx_pinctrl_irq_bus_sync_unlockfunction stmfx_gpio_irq_request_resourcesfunction stmfx_gpio_irq_release_resourcesfunction stmfx_pinctrl_irq_toggle_triggerfunction stmfx_pinctrl_irq_thread_fnfunction stmfx_pinctrl_irq_print_chipfunction stmfx_pinctrl_gpio_function_enablefunction stmfx_pinctrl_probefunction stmfx_pinctrl_removefunction stmfx_pinctrl_backup_regsfunction stmfx_pinctrl_restore_regsfunction stmfx_pinctrl_suspendfunction stmfx_pinctrl_resume
Annotated Snippet
struct stmfx_pinctrl {
struct device *dev;
struct stmfx *stmfx;
struct pinctrl_dev *pctl_dev;
struct pinctrl_desc pctl_desc;
struct gpio_chip gpio_chip;
struct mutex lock; /* IRQ bus lock */
unsigned long gpio_valid_mask;
/* Cache of IRQ_GPI_* registers for bus_lock */
u8 irq_gpi_src[NR_GPIO_REGS];
u8 irq_gpi_type[NR_GPIO_REGS];
u8 irq_gpi_evt[NR_GPIO_REGS];
u8 irq_toggle_edge[NR_GPIO_REGS];
#ifdef CONFIG_PM
/* Backup of GPIO_* registers for suspend/resume */
u8 bkp_gpio_state[NR_GPIO_REGS];
u8 bkp_gpio_dir[NR_GPIO_REGS];
u8 bkp_gpio_type[NR_GPIO_REGS];
u8 bkp_gpio_pupd[NR_GPIO_REGS];
#endif
};
static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
u32 mask = get_mask(offset);
u32 value;
int ret;
ret = regmap_read(pctl->stmfx->map, reg, &value);
return ret ? ret : !!(value & mask);
}
static int stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
u32 mask = get_mask(offset);
return regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
mask, mask);
}
static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
u32 mask = get_mask(offset);
u32 val;
int ret;
ret = regmap_read(pctl->stmfx->map, reg, &val);
/*
* On stmfx, gpio pins direction is (0)input, (1)output.
*/
if (ret)
return ret;
if (val & mask)
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
u32 mask = get_mask(offset);
return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
}
static int stmfx_gpio_direction_output(struct gpio_chip *gc,
unsigned int offset, int value)
{
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
u32 mask = get_mask(offset);
int ret;
ret = stmfx_gpio_set(gc, offset, value);
if (ret)
return ret;
return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
}
Annotation
- Immediate include surface: `linux/gpio/driver.h`, `linux/interrupt.h`, `linux/mfd/stmfx.h`, `linux/module.h`, `linux/platform_device.h`, `linux/seq_file.h`, `linux/string_choices.h`, `linux/pinctrl/pinconf.h`.
- Detected declarations: `struct stmfx_pinctrl`, `function stmfx_gpio_get`, `function stmfx_gpio_set`, `function stmfx_gpio_get_direction`, `function stmfx_gpio_direction_input`, `function stmfx_gpio_direction_output`, `function stmfx_pinconf_get_pupd`, `function stmfx_pinconf_set_pupd`, `function stmfx_pinconf_get_type`, `function stmfx_pinconf_set_type`.
- Atlas domain: Driver Families / drivers/pinctrl.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.