drivers/pinctrl/qcom/pinctrl-nord.c

File Facts

System

Linux kernel

Corpus path

drivers/pinctrl/qcom/pinctrl-nord.c

Extension

.c

Size

55424 bytes

Lines

1771

Domain

Driver Families

Bucket

drivers/pinctrl

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/module.h
• linux/of.h
• linux/platform_device.h
• pinctrl-msm.h

Detected Declarations

• enum nord_functions
• function Copyright
• function nord_tlmm_probe
• function nord_tlmm_init
• function nord_tlmm_exit

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>

#include "pinctrl-msm.h"

#define REG_SIZE 0x1000
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)    \
	{                                                             \
		.grp = PINCTRL_PINGROUP("gpio" #id,                   \
					gpio##id##_pins,              \
					ARRAY_SIZE(gpio##id##_pins)), \
		.ctl_reg = REG_SIZE * id,                             \
		.io_reg = 0x4 + REG_SIZE * id,                        \
		.intr_cfg_reg = 0x8 + REG_SIZE * id,                  \
		.intr_status_reg = 0xc + REG_SIZE * id,               \
		.mux_bit = 2,                                         \
		.pull_bit = 0,                                        \
		.drv_bit = 6,                                         \
		.egpio_enable = 12,                                   \
		.egpio_present = 11,                                  \
		.oe_bit = 9,                                          \
		.in_bit = 0,                                          \
		.out_bit = 1,                                         \
		.intr_enable_bit = 0,                                 \
		.intr_status_bit = 0,                                 \
		.intr_wakeup_present_bit = 6,                         \
		.intr_wakeup_enable_bit = 7,                          \
		.intr_target_bit = 8,                                 \
		.intr_target_kpss_val = 3,                            \
		.intr_raw_status_bit = 4,                             \
		.intr_polarity_bit = 1,                               \
		.intr_detection_bit = 2,                              \
		.intr_detection_width = 2,                            \
		.funcs = (int[]){                                     \
			msm_mux_gpio, /* gpio mode */                 \
			msm_mux_##f1,                                 \
			msm_mux_##f2,                                 \
			msm_mux_##f3,                                 \
			msm_mux_##f4,                                 \
			msm_mux_##f5,                                 \
			msm_mux_##f6,                                 \
			msm_mux_##f7,                                 \
			msm_mux_##f8,                                 \
			msm_mux_##f9,                                 \
			msm_mux_##f10,                                \
			msm_mux_##f11 /* egpio mode */                \
		},                                                    \
		.nfuncs = 12,                                         \
	}

#define UFS_RESET(pg_name, ctl, io)                                  \
	{                                                            \
		.grp = PINCTRL_PINGROUP(#pg_name,                    \
					pg_name##_pins,              \
					ARRAY_SIZE(pg_name##_pins)), \
		.ctl_reg = ctl,                                      \
		.io_reg = io,                                        \
		.intr_cfg_reg = 0,                                   \
		.intr_status_reg = 0,                                \
		.mux_bit = -1,                                       \
		.pull_bit = 3,                                       \
		.drv_bit = 0,                                        \
		.oe_bit = -1,                                        \
		.in_bit = -1,                                        \
		.out_bit = 0,                                        \
		.intr_enable_bit = -1,                               \
		.intr_status_bit = -1,                               \
		.intr_target_bit = -1,                               \
		.intr_raw_status_bit = -1,                           \
		.intr_polarity_bit = -1,                             \
		.intr_detection_bit = -1,                            \
		.intr_detection_width = -1,                          \
	}

static const struct pinctrl_pin_desc nord_pins[] = {
	PINCTRL_PIN(0, "GPIO_0"),
	PINCTRL_PIN(1, "GPIO_1"),
	PINCTRL_PIN(2, "GPIO_2"),
	PINCTRL_PIN(3, "GPIO_3"),
	PINCTRL_PIN(4, "GPIO_4"),
	PINCTRL_PIN(5, "GPIO_5"),
	PINCTRL_PIN(6, "GPIO_6"),
	PINCTRL_PIN(7, "GPIO_7"),
	PINCTRL_PIN(8, "GPIO_8"),

Annotation

• Immediate include surface: `linux/module.h`, `linux/of.h`, `linux/platform_device.h`, `pinctrl-msm.h`.
• Detected declarations: `enum nord_functions`, `function Copyright`, `function nord_tlmm_probe`, `function nord_tlmm_init`, `function nord_tlmm_exit`.
• Atlas domain: Driver Families / drivers/pinctrl.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.