drivers/pinctrl/qcom/pinctrl-sdx75.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/qcom/pinctrl-sdx75.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/qcom/pinctrl-sdx75.c
Extension
.c
Size
37179 bytes
Lines
1141
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-msm.h"

#define REG_BASE	0x100000
#define REG_SIZE	0x1000

#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10)		\
	{								\
		.grp = PINCTRL_PINGROUP("gpio"#id, gpio##id##_pins,	\
			(unsigned int)ARRAY_SIZE(gpio##id##_pins)),	\
		.ctl_reg = REG_BASE + REG_SIZE * id,			\
		.io_reg = REG_BASE + 0x4 + REG_SIZE * id,		\
		.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id,		\
		.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id,	\
		.mux_bit = 2,						\
		.pull_bit = 0,						\
		.drv_bit = 6,						\
		.egpio_enable = 12,					\
		.egpio_present = 11,					\
		.oe_bit = 9,						\
		.in_bit = 0,						\
		.out_bit = 1,						\
		.intr_enable_bit = 0,					\
		.intr_status_bit = 0,					\
		.intr_target_bit = 5,					\
		.intr_target_kpss_val = 3,				\
		.intr_raw_status_bit = 4,				\
		.intr_polarity_bit = 1,					\
		.intr_detection_bit = 2,				\
		.intr_detection_width = 2,				\
		.funcs = (int[]){					\
			msm_mux_gpio, /* gpio mode */			\
			msm_mux_##f1,					\
			msm_mux_##f2,					\
			msm_mux_##f3,					\
			msm_mux_##f4,					\
			msm_mux_##f5,					\
			msm_mux_##f6,					\
			msm_mux_##f7,					\
			msm_mux_##f8,					\
			msm_mux_##f9,					\
			msm_mux_##f10					\
		},							\
		.nfuncs = 11,						\
	}

#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)			\
	{								\
		.grp = PINCTRL_PINGROUP(#pg_name, pg_name##_pins,	\
			(unsigned int)ARRAY_SIZE(pg_name##_pins)),	\
		.ctl_reg = ctl,						\
		.io_reg = 0,						\
		.intr_cfg_reg = 0,					\
		.intr_status_reg = 0,					\
		.mux_bit = -1,						\
		.pull_bit = pull,					\
		.drv_bit = drv,						\
		.oe_bit = -1,						\
		.in_bit = -1,						\
		.out_bit = -1,						\
		.intr_enable_bit = -1,					\
		.intr_status_bit = -1,					\
		.intr_target_bit = -1,					\
		.intr_raw_status_bit = -1,				\
		.intr_polarity_bit = -1,				\
		.intr_detection_bit = -1,				\
		.intr_detection_width = -1,				\
	}

static const struct pinctrl_pin_desc sdx75_pins[] = {
	PINCTRL_PIN(0, "GPIO_0"),
	PINCTRL_PIN(1, "GPIO_1"),
	PINCTRL_PIN(2, "GPIO_2"),
	PINCTRL_PIN(3, "GPIO_3"),
	PINCTRL_PIN(4, "GPIO_4"),
	PINCTRL_PIN(5, "GPIO_5"),
	PINCTRL_PIN(6, "GPIO_6"),
	PINCTRL_PIN(7, "GPIO_7"),
	PINCTRL_PIN(8, "GPIO_8"),
	PINCTRL_PIN(9, "GPIO_9"),
	PINCTRL_PIN(10, "GPIO_10"),
	PINCTRL_PIN(11, "GPIO_11"),
	PINCTRL_PIN(12, "GPIO_12"),

Annotation

Implementation Notes