drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
Source file repositories/reference/linux-study-clean/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c- Extension
.c- Size
- 38561 bytes
- Lines
- 1311
- Domain
- Driver Families
- Bucket
- drivers/pinctrl
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/gpio/driver.hlinux/interrupt.hlinux/module.hlinux/of.hlinux/of_irq.hlinux/platform_device.hlinux/regmap.hlinux/seq_file.hlinux/slab.hlinux/spmi.hlinux/string_choices.hlinux/types.hlinux/pinctrl/pinconf-generic.hlinux/pinctrl/pinconf.hlinux/pinctrl/pinmux.hdt-bindings/pinctrl/qcom,pmic-gpio.h../core.h../pinctrl-utils.h
Detected Declarations
struct pmic_gpio_padstruct pmic_gpio_stateenum pmic_gpio_func_indexfunction pmic_gpio_readfunction pmic_gpio_writefunction pmic_gpio_get_groups_countfunction pmic_gpio_get_group_pinsfunction pmic_gpio_get_functions_countfunction pmic_gpio_get_function_groupsfunction pmic_gpio_set_muxfunction pmic_gpio_config_getfunction pmic_gpio_config_setfunction pmic_gpio_config_dbg_showfunction pmic_gpio_get_directionfunction pmic_gpio_direction_inputfunction pmic_gpio_direction_outputfunction pmic_gpio_getfunction pmic_gpio_setfunction pmic_gpio_of_xlatefunction pmic_gpio_dbg_showfunction pmic_gpio_populatefunction pmic_gpio_domain_translatefunction pmic_gpio_child_offset_to_irqfunction pmic_gpio_child_to_parent_hwirqfunction pmic_gpio_populate_parent_fwspecfunction pmic_gpio_irq_maskfunction pmic_gpio_irq_unmaskfunction pmic_gpio_probefunction gpiochip_add_pin_rangefunction pmic_gpio_remove
Annotated Snippet
struct pmic_gpio_pad {
u16 base;
bool is_enabled;
bool out_value;
bool have_buffer;
bool output_enabled;
bool input_enabled;
bool analog_pass;
bool lv_mv_type;
unsigned int num_sources;
unsigned int power_source;
unsigned int buffer_type;
unsigned int pullup;
unsigned int strength;
unsigned int function;
unsigned int atest;
unsigned int dtest_buffer;
};
struct pmic_gpio_state {
struct device *dev;
struct regmap *map;
struct pinctrl_dev *ctrl;
struct gpio_chip chip;
u8 usid;
u8 pid_base;
};
static const struct pinconf_generic_params pmic_gpio_bindings[] = {
{"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
{"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
{"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
{"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
{"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
};
#endif
static const char *const pmic_gpio_groups[] = {
"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
};
static const char *const pmic_gpio_functions[] = {
[PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
[PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
[PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
[PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
[PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
[PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
[PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
[PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
[PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
[PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
};
static int pmic_gpio_read(struct pmic_gpio_state *state,
struct pmic_gpio_pad *pad, unsigned int addr)
{
unsigned int val;
int ret;
ret = regmap_read(state->map, pad->base + addr, &val);
if (ret < 0)
dev_err(state->dev, "read 0x%x failed\n", addr);
else
ret = val;
return ret;
}
static int pmic_gpio_write(struct pmic_gpio_state *state,
struct pmic_gpio_pad *pad, unsigned int addr,
unsigned int val)
{
int ret;
ret = regmap_write(state->map, pad->base + addr, val);
if (ret < 0)
Annotation
- Immediate include surface: `linux/gpio/driver.h`, `linux/interrupt.h`, `linux/module.h`, `linux/of.h`, `linux/of_irq.h`, `linux/platform_device.h`, `linux/regmap.h`, `linux/seq_file.h`.
- Detected declarations: `struct pmic_gpio_pad`, `struct pmic_gpio_state`, `enum pmic_gpio_func_index`, `function pmic_gpio_read`, `function pmic_gpio_write`, `function pmic_gpio_get_groups_count`, `function pmic_gpio_get_group_pins`, `function pmic_gpio_get_functions_count`, `function pmic_gpio_get_function_groups`, `function pmic_gpio_set_mux`.
- Atlas domain: Driver Families / drivers/pinctrl.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.