drivers/pinctrl/renesas/pfc-r8a77990.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/renesas/pfc-r8a77990.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/renesas/pfc-r8a77990.c
Extension
.c
Size
161450 bytes
Lines
5341
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * R8A77990 processor support - PFC hardware block.
 *
 * Copyright (C) 2018-2019 Renesas Electronics Corp.
 *
 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
 *
 * R8A7796 processor support - PFC hardware block.
 *
 * Copyright (C) 2016-2017 Renesas Electronics Corp.
 */

#include <linux/errno.h>
#include <linux/kernel.h>

#include "sh_pfc.h"

#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)

#define CPU_ALL_GP(fn, sfx) \
	PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
	PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
	PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
	PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)

#define CPU_ALL_NOGP(fn)						\
	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
	PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS),	\
	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),		\
	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),		\
	PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),		\
	PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP),	\
	PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)

/*
 * F_() : just information
 * FM() : macro for FN_xxx / xxx_MARK
 */

/* GPSR0 */
#define GPSR0_17	F_(SDA4,		IP7_27_24)
#define GPSR0_16	F_(SCL4,		IP7_23_20)
#define GPSR0_15	F_(D15,			IP7_19_16)
#define GPSR0_14	F_(D14,			IP7_15_12)
#define GPSR0_13	F_(D13,			IP7_11_8)
#define GPSR0_12	F_(D12,			IP7_7_4)
#define GPSR0_11	F_(D11,			IP7_3_0)
#define GPSR0_10	F_(D10,			IP6_31_28)
#define GPSR0_9		F_(D9,			IP6_27_24)
#define GPSR0_8		F_(D8,			IP6_23_20)
#define GPSR0_7		F_(D7,			IP6_19_16)
#define GPSR0_6		F_(D6,			IP6_15_12)
#define GPSR0_5		F_(D5,			IP6_11_8)
#define GPSR0_4		F_(D4,			IP6_7_4)
#define GPSR0_3		F_(D3,			IP6_3_0)
#define GPSR0_2		F_(D2,			IP5_31_28)
#define GPSR0_1		F_(D1,			IP5_27_24)
#define GPSR0_0		F_(D0,			IP5_23_20)

/* GPSR1 */
#define GPSR1_22	F_(WE0_N,		IP5_19_16)
#define GPSR1_21	F_(CS0_N,		IP5_15_12)
#define GPSR1_20	FM(CLKOUT)

Annotation

Implementation Notes