drivers/pinctrl/renesas/pfc-r8a77995.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/renesas/pfc-r8a77995.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/renesas/pfc-r8a77995.c
Extension
.c
Size
103157 bytes
Lines
3195
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * R8A77995 processor support - PFC hardware block.
 *
 * Copyright (C) 2017 Renesas Electronics Corp.
 *
 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
 *
 * R-Car Gen3 processor support - PFC hardware block.
 *
 * Copyright (C) 2015  Renesas Electronics Corporation
 */

#include <linux/errno.h>
#include <linux/kernel.h>

#include "core.h"
#include "sh_pfc.h"

#define CPU_ALL_GP(fn, sfx)						\
	PORT_GP_CFG_9(0,  fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)

#define CPU_ALL_NOGP(fn)						\
	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN),	\
	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),		\
	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),		\
	PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),		\
	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP),	\
	PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)

/*
 * F_() : just information
 * FM() : macro for FN_xxx / xxx_MARK
 */

/* GPSR0 */
#define GPSR0_8		F_(MLB_SIG,		IP0_27_24)
#define GPSR0_7		F_(MLB_DAT,		IP0_23_20)
#define GPSR0_6		F_(MLB_CLK,		IP0_19_16)
#define GPSR0_5		F_(MSIOF2_RXD,		IP0_15_12)
#define GPSR0_4		F_(MSIOF2_TXD,		IP0_11_8)
#define GPSR0_3		F_(MSIOF2_SCK,		IP0_7_4)
#define GPSR0_2		F_(IRQ0_A,		IP0_3_0)
#define GPSR0_1		FM(USB0_OVC)
#define GPSR0_0		FM(USB0_PWEN)

/* GPSR1 */
#define GPSR1_31	F_(QPOLB,		IP4_27_24)
#define GPSR1_30	F_(QPOLA,		IP4_23_20)
#define GPSR1_29	F_(DU_CDE,		IP4_19_16)
#define GPSR1_28	F_(DU_DISP_CDE,		IP4_15_12)
#define GPSR1_27	F_(DU_DISP,		IP4_11_8)
#define GPSR1_26	F_(DU_VSYNC,		IP4_7_4)
#define GPSR1_25	F_(DU_HSYNC,		IP4_3_0)
#define GPSR1_24	F_(DU_DOTCLKOUT0,	IP3_31_28)
#define GPSR1_23	F_(DU_DR7,		IP3_27_24)
#define GPSR1_22	F_(DU_DR6,		IP3_23_20)
#define GPSR1_21	F_(DU_DR5,		IP3_19_16)
#define GPSR1_20	F_(DU_DR4,		IP3_15_12)
#define GPSR1_19	F_(DU_DR3,		IP3_11_8)
#define GPSR1_18	F_(DU_DR2,		IP3_7_4)
#define GPSR1_17	F_(DU_DR1,		IP3_3_0)
#define GPSR1_16	F_(DU_DR0,		IP2_31_28)
#define GPSR1_15	F_(DU_DG7,		IP2_27_24)
#define GPSR1_14	F_(DU_DG6,		IP2_23_20)
#define GPSR1_13	F_(DU_DG5,		IP2_19_16)
#define GPSR1_12	F_(DU_DG4,		IP2_15_12)
#define GPSR1_11	F_(DU_DG3,		IP2_11_8)
#define GPSR1_10	F_(DU_DG2,		IP2_7_4)
#define GPSR1_9		F_(DU_DG1,		IP2_3_0)
#define GPSR1_8		F_(DU_DG0,		IP1_31_28)
#define GPSR1_7		F_(DU_DB7,		IP1_27_24)
#define GPSR1_6		F_(DU_DB6,		IP1_23_20)
#define GPSR1_5		F_(DU_DB5,		IP1_19_16)
#define GPSR1_4		F_(DU_DB4,		IP1_15_12)
#define GPSR1_3		F_(DU_DB3,		IP1_11_8)
#define GPSR1_2		F_(DU_DB2,		IP1_7_4)
#define GPSR1_1		F_(DU_DB1,		IP1_3_0)
#define GPSR1_0		F_(DU_DB0,		IP0_31_28)

/* GPSR2 */

Annotation

Implementation Notes