drivers/pinctrl/renesas/pfc-r8a779a0.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/renesas/pfc-r8a779a0.c

File Facts

System: Linux kernel
Corpus path: drivers/pinctrl/renesas/pfc-r8a779a0.c
Extension: .c
Size: 146694 bytes
Lines: 4383
Domain: Driver Families
Bucket: drivers/pinctrl
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/errno.h
linux/io.h
linux/kernel.h
sh_pfc.h

Detected Declarations

enum ioctrl_regs
function r8a779a0_pin_to_pocctrl

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * R8A779A0 processor support - PFC hardware block.
 *
 * Copyright (C) 2020 Renesas Electronics Corp.
 *
 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
 */

#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>

#include "sh_pfc.h"

#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)

#define CPU_ALL_GP(fn, sfx)	\
	PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS),					\
	PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
	PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS)

#define CPU_ALL_NOGP(fn)									\

Annotation

Immediate include surface: `linux/errno.h`, `linux/io.h`, `linux/kernel.h`, `sh_pfc.h`.
Detected declarations: `enum ioctrl_regs`, `function r8a779a0_pin_to_pocctrl`.
Atlas domain: Driver Families / drivers/pinctrl.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.