drivers/pinctrl/renesas/pfc-r8a779f0.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/renesas/pfc-r8a779f0.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/renesas/pfc-r8a779f0.c
Extension
.c
Size
63038 bytes
Lines
2103
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * R8A779F0 processor support - PFC hardware block.
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 *
 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
 */

#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>

#include "sh_pfc.h"

#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)

#define CPU_ALL_GP(fn, sfx)	\
	PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
	PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS),	\
	PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)

#define CPU_ALL_NOGP(fn)								\
	PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN),	\
	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)

/*
 * F_() : just information
 * FM() : macro for FN_xxx / xxx_MARK
 */

/* GPSR0 */
#define GPSR0_20	F_(IRQ3,	IP2SR0_19_16)
#define GPSR0_19	F_(IRQ2,	IP2SR0_15_12)
#define GPSR0_18	F_(IRQ1,	IP2SR0_11_8)
#define GPSR0_17	F_(IRQ0,	IP2SR0_7_4)
#define GPSR0_16	F_(MSIOF0_SS2,	IP2SR0_3_0)
#define GPSR0_15	F_(MSIOF0_SS1,	IP1SR0_31_28)
#define GPSR0_14	F_(MSIOF0_SCK,	IP1SR0_27_24)
#define GPSR0_13	F_(MSIOF0_TXD,	IP1SR0_23_20)
#define GPSR0_12	F_(MSIOF0_RXD,	IP1SR0_19_16)
#define GPSR0_11	F_(MSIOF0_SYNC,	IP1SR0_15_12)
#define GPSR0_10	F_(CTS0_N,	IP1SR0_11_8)
#define GPSR0_9		F_(RTS0_N,	IP1SR0_7_4)
#define GPSR0_8		F_(SCK0,	IP1SR0_3_0)
#define GPSR0_7		F_(TX0,		IP0SR0_31_28)
#define GPSR0_6		F_(RX0,		IP0SR0_27_24)
#define GPSR0_5		F_(HRTS0_N,	IP0SR0_23_20)
#define GPSR0_4		F_(HCTS0_N,	IP0SR0_19_16)
#define GPSR0_3		F_(HTX0,	IP0SR0_15_12)
#define GPSR0_2		F_(HRX0,	IP0SR0_11_8)
#define GPSR0_1		F_(HSCK0,	IP0SR0_7_4)
#define GPSR0_0		F_(SCIF_CLK,	IP0SR0_3_0)

/* GPSR1 */
#define GPSR1_24	FM(SD_WP)
#define GPSR1_23	FM(SD_CD)
#define GPSR1_22	FM(MMC_SD_CMD)
#define GPSR1_21	FM(MMC_D7)
#define GPSR1_20	FM(MMC_DS)
#define GPSR1_19	FM(MMC_D6)
#define GPSR1_18	FM(MMC_D4)
#define GPSR1_17	FM(MMC_D5)
#define GPSR1_16	FM(MMC_SD_D3)
#define GPSR1_15	FM(MMC_SD_D2)
#define GPSR1_14	FM(MMC_SD_D1)
#define GPSR1_13	FM(MMC_SD_D0)
#define GPSR1_12	FM(MMC_SD_CLK)
#define GPSR1_11	FM(GP1_11)
#define GPSR1_10	FM(GP1_10)
#define GPSR1_9		FM(GP1_09)
#define GPSR1_8		FM(GP1_08)
#define GPSR1_7		F_(GP1_07,	IP0SR1_31_28)
#define GPSR1_6		F_(GP1_06,	IP0SR1_27_24)
#define GPSR1_5		F_(GP1_05,	IP0SR1_23_20)
#define GPSR1_4		F_(GP1_04,	IP0SR1_19_16)
#define GPSR1_3		F_(GP1_03,	IP0SR1_15_12)
#define GPSR1_2		F_(GP1_02,	IP0SR1_11_8)
#define GPSR1_1		F_(GP1_01,	IP0SR1_7_4)
#define GPSR1_0		F_(GP1_00,	IP0SR1_3_0)

/* GPSR2 */
#define GPSR2_16	FM(PCIE1_CLKREQ_N)
#define GPSR2_15	FM(PCIE0_CLKREQ_N)
#define GPSR2_14	FM(QSPI0_IO3)
#define GPSR2_13	FM(QSPI0_SSL)
#define GPSR2_12	FM(QSPI0_MISO_IO1)
#define GPSR2_11	FM(QSPI0_IO2)
#define GPSR2_10	FM(QSPI0_SPCLK)

Annotation

Implementation Notes