drivers/pinctrl/renesas/pfc-sh73a0.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/renesas/pfc-sh73a0.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/renesas/pfc-sh73a0.c
Extension
.c
Size
124902 bytes
Lines
4174
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * sh73a0 processor support - PFC hardware block
 *
 * Copyright (C) 2010 Renesas Solutions Corp.
 * Copyright (C) 2010 NISHIMOTO Hiroki
 */
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/slab.h>

#include "sh_pfc.h"

#define CPU_ALL_PORT(fn, pfx, sfx)					\
	PORT_10(0,  fn, pfx, sfx), PORT_90(0, fn, pfx, sfx),		\
	PORT_10(100, fn, pfx##10, sfx),					\
	PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx),	\
	PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx),	\
	PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx),	\
	PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx),	\
	PORT_1(118, fn, pfx##118, sfx),					\
	PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx),	\
	PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx),	\
	PORT_10(150, fn, pfx##15, sfx),					\
	PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx),	\
	PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx),	\
	PORT_1(164, fn, pfx##164, sfx),					\
	PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx),	\
	PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx),	\
	PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx),	\
	PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx),	\
	PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx),	\
	PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx),	\
	PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx),	\
	PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx),	\
	PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx),	\
	PORT_1(282, fn, pfx##282, sfx),					\
	PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx),	\
	PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)

#define CPU_ALL_NOGP(fn)	\
	PIN_NOGP(A11, "F26", fn)

enum {
	PINMUX_RESERVED = 0,

	PINMUX_DATA_BEGIN,
	PORT_ALL(DATA),			/* PORT0_DATA -> PORT309_DATA */
	PINMUX_DATA_END,

	PINMUX_INPUT_BEGIN,
	PORT_ALL(IN),			/* PORT0_IN -> PORT309_IN */
	PINMUX_INPUT_END,

	PINMUX_OUTPUT_BEGIN,
	PORT_ALL(OUT),			/* PORT0_OUT -> PORT309_OUT */
	PINMUX_OUTPUT_END,

	PINMUX_FUNCTION_BEGIN,
	PORT_ALL(FN_IN),		/* PORT0_FN_IN -> PORT309_FN_IN */
	PORT_ALL(FN_OUT),		/* PORT0_FN_OUT -> PORT309_FN_OUT */
	PORT_ALL(FN0),			/* PORT0_FN0 -> PORT309_FN0 */
	PORT_ALL(FN1),			/* PORT0_FN1 -> PORT309_FN1 */
	PORT_ALL(FN2),			/* PORT0_FN2 -> PORT309_FN2 */
	PORT_ALL(FN3),			/* PORT0_FN3 -> PORT309_FN3 */
	PORT_ALL(FN4),			/* PORT0_FN4 -> PORT309_FN4 */
	PORT_ALL(FN5),			/* PORT0_FN5 -> PORT309_FN5 */
	PORT_ALL(FN6),			/* PORT0_FN6 -> PORT309_FN6 */
	PORT_ALL(FN7),			/* PORT0_FN7 -> PORT309_FN7 */

	MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
	MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
	MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
	MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
	MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
	MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
	MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
	MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
	MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
	MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
	MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
	MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
	MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
	MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
	MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
	MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,

Annotation

Implementation Notes