drivers/pinctrl/renesas/sh_pfc.h

Source file repositories/reference/linux-study-clean/drivers/pinctrl/renesas/sh_pfc.h

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/renesas/sh_pfc.h
Extension
.h
Size
26754 bytes
Lines
778
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sh_pfc_pin {
	const char *name;
	unsigned int configs;
	u16 pin;
	u16 enum_id;
};

#define SH_PFC_PIN_GROUP_ALIAS(alias, _name) {				\
	.name = #alias,							\
	.pins = _name##_pins,						\
	.mux = _name##_mux,						\
	.nr_pins = ARRAY_SIZE(_name##_pins) +				\
	BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)),	\
}
#define SH_PFC_PIN_GROUP(name)	SH_PFC_PIN_GROUP_ALIAS(name, name)

/*
 * Define a pin group referring to a subset of an array of pins.
 */
#define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) {		\
	.name = #_name,							\
	.pins = data##_pins + first,					\
	.mux = data##_mux + first,					\
	.nr_pins = n +							\
	BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) +	\
	BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)),		\
}

/*
 * Define a pin group for the data pins of a resizable bus.
 * An optional 'suffix' argument is accepted, to be used when the same group
 * can appear on a different set of pins.
 */
#define BUS_DATA_PIN_GROUP(base, n, ...)				\
	SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n)

struct sh_pfc_pin_group {
	const char *name;
	const unsigned int *pins;
	const unsigned int *mux;
	unsigned int nr_pins;
};

#define SH_PFC_FUNCTION(n) {						\
	.name = #n,							\
	.groups = n##_groups,						\
	.nr_groups = ARRAY_SIZE(n##_groups),				\
}

struct sh_pfc_function {
	const char *name;
	const char * const *groups;
	unsigned int nr_groups;
};

struct pinmux_func {
	u16 enum_id;
	const char *name;
};

struct pinmux_cfg_reg {
	u32 reg;
	u8 reg_width, field_width;
#ifdef DEBUG
	u16 nr_enum_ids;	/* for variable width regs only */
#define SET_NR_ENUM_IDS(n)	.nr_enum_ids = n,
#else
#define SET_NR_ENUM_IDS(n)
#endif
	const u16 *enum_ids;
	const s8 *var_field_width;
};

#define GROUP(...)	__VA_ARGS__

/*
 * Describe a config register consisting of several fields of the same width
 *   - name: Register name (unused, for documentation purposes only)
 *   - r: Physical register address
 *   - r_width: Width of the register (in bits)
 *   - f_width: Width of the fixed-width register fields (in bits)
 *   - ids: For each register field (from left to right, i.e. MSB to LSB),
 *          2^f_width enum IDs must be specified, one for each possible
 *          combination of the register field bit values, all wrapped using
 *          the GROUP() macro.
 */
#define PINMUX_CFG_REG(name, r, r_width, f_width, ids)			\
	.reg = r, .reg_width = r_width,					\
	.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) +	\
	BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \

Annotation

Implementation Notes