drivers/pinctrl/spear/pinctrl-spear1310.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/spear/pinctrl-spear1310.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/spear/pinctrl-spear1310.c
Extension
.c
Size
77755 bytes
Lines
2719
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/err.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"

#define DRIVER_NAME "spear1310-pinmux"

/* pins */
static const struct pinctrl_pin_desc spear1310_pins[] = {
	SPEAR_PIN_0_TO_101,
	SPEAR_PIN_102_TO_245,
};

/* registers */
#define PERIP_CFG					0x3B0
	#define MCIF_SEL_SHIFT				5
	#define MCIF_SEL_SD				(0x1 << MCIF_SEL_SHIFT)
	#define MCIF_SEL_CF				(0x2 << MCIF_SEL_SHIFT)
	#define MCIF_SEL_XD				(0x3 << MCIF_SEL_SHIFT)
	#define MCIF_SEL_MASK				(0x3 << MCIF_SEL_SHIFT)

#define PCIE_SATA_CFG					0x3A4
	#define PCIE_SATA2_SEL_PCIE			(0 << 31)
	#define PCIE_SATA1_SEL_PCIE			(0 << 30)
	#define PCIE_SATA0_SEL_PCIE			(0 << 29)
	#define PCIE_SATA2_SEL_SATA			(1 << 31)
	#define PCIE_SATA1_SEL_SATA			(1 << 30)
	#define PCIE_SATA0_SEL_SATA			(1 << 29)
	#define SATA2_CFG_TX_CLK_EN			(1 << 27)
	#define SATA2_CFG_RX_CLK_EN			(1 << 26)
	#define SATA2_CFG_POWERUP_RESET			(1 << 25)
	#define SATA2_CFG_PM_CLK_EN			(1 << 24)
	#define SATA1_CFG_TX_CLK_EN			(1 << 23)
	#define SATA1_CFG_RX_CLK_EN			(1 << 22)
	#define SATA1_CFG_POWERUP_RESET			(1 << 21)
	#define SATA1_CFG_PM_CLK_EN			(1 << 20)
	#define SATA0_CFG_TX_CLK_EN			(1 << 19)
	#define SATA0_CFG_RX_CLK_EN			(1 << 18)
	#define SATA0_CFG_POWERUP_RESET			(1 << 17)
	#define SATA0_CFG_PM_CLK_EN			(1 << 16)
	#define PCIE2_CFG_DEVICE_PRESENT		(1 << 11)
	#define PCIE2_CFG_POWERUP_RESET			(1 << 10)
	#define PCIE2_CFG_CORE_CLK_EN			(1 << 9)
	#define PCIE2_CFG_AUX_CLK_EN			(1 << 8)
	#define PCIE1_CFG_DEVICE_PRESENT		(1 << 7)
	#define PCIE1_CFG_POWERUP_RESET			(1 << 6)
	#define PCIE1_CFG_CORE_CLK_EN			(1 << 5)
	#define PCIE1_CFG_AUX_CLK_EN			(1 << 4)
	#define PCIE0_CFG_DEVICE_PRESENT		(1 << 3)
	#define PCIE0_CFG_POWERUP_RESET			(1 << 2)
	#define PCIE0_CFG_CORE_CLK_EN			(1 << 1)
	#define PCIE0_CFG_AUX_CLK_EN			(1 << 0)

#define PAD_FUNCTION_EN_0				0x650
	#define PMX_UART0_MASK				(1 << 1)
	#define PMX_I2C0_MASK				(1 << 2)
	#define PMX_I2S0_MASK				(1 << 3)
	#define PMX_SSP0_MASK				(1 << 4)
	#define PMX_CLCD1_MASK				(1 << 5)
	#define PMX_EGPIO00_MASK			(1 << 6)
	#define PMX_EGPIO01_MASK			(1 << 7)
	#define PMX_EGPIO02_MASK			(1 << 8)
	#define PMX_EGPIO03_MASK			(1 << 9)
	#define PMX_EGPIO04_MASK			(1 << 10)
	#define PMX_EGPIO05_MASK			(1 << 11)
	#define PMX_EGPIO06_MASK			(1 << 12)
	#define PMX_EGPIO07_MASK			(1 << 13)
	#define PMX_EGPIO08_MASK			(1 << 14)
	#define PMX_EGPIO09_MASK			(1 << 15)
	#define PMX_SMI_MASK				(1 << 16)
	#define PMX_NAND8_MASK				(1 << 17)
	#define PMX_GMIICLK_MASK			(1 << 18)
	#define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK	(1 << 19)
	#define PMX_RXCLK_RDV_TXEN_D03_MASK		(1 << 20)
	#define PMX_GMIID47_MASK			(1 << 21)
	#define PMX_MDC_MDIO_MASK			(1 << 22)
	#define PMX_MCI_DATA8_15_MASK			(1 << 23)
	#define PMX_NFAD23_MASK				(1 << 24)
	#define PMX_NFAD24_MASK				(1 << 25)
	#define PMX_NFAD25_MASK				(1 << 26)
	#define PMX_NFCE3_MASK				(1 << 27)
	#define PMX_NFWPRT3_MASK			(1 << 28)
	#define PMX_NFRSTPWDWN0_MASK			(1 << 29)
	#define PMX_NFRSTPWDWN1_MASK			(1 << 30)
	#define PMX_NFRSTPWDWN2_MASK			(1 << 31)

#define PAD_FUNCTION_EN_1				0x654
	#define PMX_NFRSTPWDWN3_MASK			(1 << 0)
	#define PMX_SMINCS2_MASK			(1 << 1)

Annotation

Implementation Notes