drivers/pinctrl/spear/pinctrl-spear1340.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/spear/pinctrl-spear1340.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/spear/pinctrl-spear1340.c
Extension
.c
Size
50421 bytes
Lines
2035
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/err.h>
#include <linux/init.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"

#define DRIVER_NAME "spear1340-pinmux"

/* pins */
static const struct pinctrl_pin_desc spear1340_pins[] = {
	SPEAR_PIN_0_TO_101,
	SPEAR_PIN_102_TO_245,
	PINCTRL_PIN(246, "PLGPIO246"),
	PINCTRL_PIN(247, "PLGPIO247"),
	PINCTRL_PIN(248, "PLGPIO248"),
	PINCTRL_PIN(249, "PLGPIO249"),
	PINCTRL_PIN(250, "PLGPIO250"),
	PINCTRL_PIN(251, "PLGPIO251"),
};

/* In SPEAr1340 there are two levels of pad muxing */
/* - pads as gpio OR peripherals */
#define PAD_FUNCTION_EN_1			0x668
#define PAD_FUNCTION_EN_2			0x66C
#define PAD_FUNCTION_EN_3			0x670
#define PAD_FUNCTION_EN_4			0x674
#define PAD_FUNCTION_EN_5			0x690
#define PAD_FUNCTION_EN_6			0x694
#define PAD_FUNCTION_EN_7			0x698
#define PAD_FUNCTION_EN_8			0x69C

/* - If peripherals, then primary OR alternate peripheral */
#define PAD_SHARED_IP_EN_1			0x6A0
#define PAD_SHARED_IP_EN_2			0x6A4

/*
 * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8
 * registers with 32 bits each for handling gpio pads, register 8 has only 26
 * relevant bits.
 */
/* macro's for making pads as gpio's */
#define PADS_AS_GPIO_REG0_MASK			0xFFFFFFFE
#define PADS_AS_GPIO_REGS_MASK			0xFFFFFFFF
#define PADS_AS_GPIO_REG7_MASK			0x07FFFFFF

/* macro's for making pads as peripherals */
#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK	0x00000FFE
#define UART0_ENH_AND_GPT_REG0_MASK		0x0003F000
#define PWM1_AND_KBD_COL5_REG0_MASK		0x00040000
#define I2C1_REG0_MASK				0x01080000
#define SPDIF_IN_REG0_MASK			0x00100000
#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK	0x00400000
#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK	0x00800000
#define PWM0_AND_SSP0_CS1_REG0_MASK		0x02000000
#define VIP_AND_CAM3_REG0_MASK			0xFC200000
#define VIP_AND_CAM3_REG1_MASK			0x0000000F
#define VIP_REG1_MASK				0x00001EF0
#define VIP_AND_CAM2_REG1_MASK			0x007FE100
#define VIP_AND_CAM1_REG1_MASK			0xFF800000
#define VIP_AND_CAM1_REG2_MASK			0x00000003
#define VIP_AND_CAM0_REG2_MASK			0x00001FFC
#define SMI_REG2_MASK				0x0021E000
#define SSP0_REG2_MASK				0x001E0000
#define TS_AND_SSP0_CS2_REG2_MASK		0x00400000
#define UART0_REG2_MASK				0x01800000
#define UART1_REG2_MASK				0x06000000
#define I2S_IN_REG2_MASK			0xF8000000
#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK	0x000001FE
#define I2S_OUT_REG3_MASK			0x000001EF
#define I2S_IN_REG3_MASK			0x00000010
#define GMAC_REG3_MASK				0xFFFFFE00
#define GMAC_REG4_MASK				0x0000001F
#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK	0x7FFFFF20
#define SSP0_CS3_REG4_MASK			0x00000020
#define I2C0_REG4_MASK				0x000000C0
#define CEC0_REG4_MASK				0x00000100
#define CEC1_REG4_MASK				0x00000200
#define SPDIF_OUT_REG4_MASK			0x00000400
#define CLCD_REG4_MASK				0x7FFFF800
#define CLCD_AND_ARM_TRACE_REG4_MASK		0x80000000
#define CLCD_AND_ARM_TRACE_REG5_MASK		0xFFFFFFFF
#define CLCD_AND_ARM_TRACE_REG6_MASK		0x00000001
#define FSMC_PNOR_AND_MCIF_REG6_MASK		0x073FFFFE
#define MCIF_REG6_MASK				0xF8C00000
#define MCIF_REG7_MASK				0x000043FF
#define FSMC_8BIT_REG7_MASK			0x07FFBC00

/* other registers */
#define PERIP_CFG				0x42C
	/* PERIP_CFG register masks */

Annotation

Implementation Notes