drivers/pinctrl/sunplus/sppctl.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/sunplus/sppctl.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/sunplus/sppctl.c
Extension
.c
Size
32494 bytes
Lines
1130
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sppctl_gpio_chip {
	void __iomem *gpioxt_base;	/* MASTER, OE, OUT, IN, I_INV, O_INV, OD */
	void __iomem *first_base;	/* GPIO_FIRST                            */

	struct gpio_chip chip;
	spinlock_t lock;		/* lock for accessing OE register        */
};

static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
	return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
}

static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
{
	writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
}

static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
	return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
}

static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
					     u32 off)
{
	writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
}

static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
	return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
}

static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
{
	writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
}

static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
{
	writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off);
}

static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
	return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off);
}

static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
	return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
}

static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
					   u32 off)
{
	writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
}

static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
	return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
}

static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
					   u32 off)
{
	writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
}

static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
{
	return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
}

static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
{
	writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
}

static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
{
	u32 bit_off;

	/* Each register has 32 bits. */
	*reg_off = (offset / 32) * 4;
	bit_off = offset % 32;

	return bit_off;

Annotation

Implementation Notes