drivers/pinctrl/tegra/pinctrl-tegra186.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/tegra/pinctrl-tegra186.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/tegra/pinctrl-tegra186.c
Extension
.c
Size
87016 bytes
Lines
1980
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Pinctrl data for the NVIDIA Tegra186 pinmux
 *
 * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#include "pinctrl-tegra.h"

/* Define unique ID for each pins */
enum {
	TEGRA_PIN_PEX_L0_RST_N_PA0,
	TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
	TEGRA_PIN_PEX_WAKE_N_PA2,
	TEGRA_PIN_PEX_L1_RST_N_PA3,
	TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
	TEGRA_PIN_PEX_L2_RST_N_PA5,
	TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
	TEGRA_PIN_UART4_TX_PB0,
	TEGRA_PIN_UART4_RX_PB1,
	TEGRA_PIN_UART4_RTS_PB2,
	TEGRA_PIN_UART4_CTS_PB3,
	TEGRA_PIN_GPIO_WAN1_PB4,
	TEGRA_PIN_GPIO_WAN2_PB5,
	TEGRA_PIN_GPIO_WAN3_PB6,
	TEGRA_PIN_GPIO_WAN4_PC0,
	TEGRA_PIN_DAP2_SCLK_PC1,
	TEGRA_PIN_DAP2_DOUT_PC2,
	TEGRA_PIN_DAP2_DIN_PC3,
	TEGRA_PIN_DAP2_FS_PC4,
	TEGRA_PIN_GEN1_I2C_SCL_PC5,
	TEGRA_PIN_GEN1_I2C_SDA_PC6,
	TEGRA_PIN_SDMMC1_CLK_PD0,
	TEGRA_PIN_SDMMC1_CMD_PD1,
	TEGRA_PIN_SDMMC1_DAT0_PD2,
	TEGRA_PIN_SDMMC1_DAT1_PD3,
	TEGRA_PIN_SDMMC1_DAT2_PD4,
	TEGRA_PIN_SDMMC1_DAT3_PD5,
	TEGRA_PIN_EQOS_TXC_PE0,
	TEGRA_PIN_EQOS_TD0_PE1,
	TEGRA_PIN_EQOS_TD1_PE2,
	TEGRA_PIN_EQOS_TD2_PE3,
	TEGRA_PIN_EQOS_TD3_PE4,
	TEGRA_PIN_EQOS_TX_CTL_PE5,
	TEGRA_PIN_EQOS_RD0_PE6,
	TEGRA_PIN_EQOS_RD1_PE7,
	TEGRA_PIN_EQOS_RD2_PF0,
	TEGRA_PIN_EQOS_RD3_PF1,
	TEGRA_PIN_EQOS_RX_CTL_PF2,
	TEGRA_PIN_EQOS_RXC_PF3,
	TEGRA_PIN_EQOS_MDIO_PF4,
	TEGRA_PIN_EQOS_MDC_PF5,
	TEGRA_PIN_SDMMC3_CLK_PG0,
	TEGRA_PIN_SDMMC3_CMD_PG1,
	TEGRA_PIN_SDMMC3_DAT0_PG2,
	TEGRA_PIN_SDMMC3_DAT1_PG3,
	TEGRA_PIN_SDMMC3_DAT2_PG4,
	TEGRA_PIN_SDMMC3_DAT3_PG5,
	TEGRA_PIN_GPIO_WAN5_PH0,
	TEGRA_PIN_GPIO_WAN6_PH1,
	TEGRA_PIN_GPIO_WAN7_PH2,
	TEGRA_PIN_GPIO_WAN8_PH3,
	TEGRA_PIN_BCPU_PWR_REQ_PH4,
	TEGRA_PIN_MCPU_PWR_REQ_PH5,
	TEGRA_PIN_GPU_PWR_REQ_PH6,
	TEGRA_PIN_GPIO_PQ0_PI0,
	TEGRA_PIN_GPIO_PQ1_PI1,
	TEGRA_PIN_GPIO_PQ2_PI2,
	TEGRA_PIN_GPIO_PQ3_PI3,
	TEGRA_PIN_GPIO_PQ4_PI4,
	TEGRA_PIN_GPIO_PQ5_PI5,
	TEGRA_PIN_GPIO_PQ6_PI6,
	TEGRA_PIN_GPIO_PQ7_PI7,
	TEGRA_PIN_DAP1_SCLK_PJ0,
	TEGRA_PIN_DAP1_DOUT_PJ1,

Annotation

Implementation Notes