drivers/pinctrl/tegra/pinctrl-tegra234.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/tegra/pinctrl-tegra234.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/tegra/pinctrl-tegra234.c
Extension
.c
Size
79911 bytes
Lines
1961
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Pinctrl data for the NVIDIA Tegra234 pinmux
 *
 * Copyright (c) 2021-2023, NVIDIA CORPORATION.  All rights reserved.
 */

#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>

#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#include "pinctrl-tegra.h"

/* Define unique ID for each pins */
enum {
	TEGRA_PIN_DAP6_SCLK_PA0,
	TEGRA_PIN_DAP6_DOUT_PA1,
	TEGRA_PIN_DAP6_DIN_PA2,
	TEGRA_PIN_DAP6_FS_PA3,
	TEGRA_PIN_DAP4_SCLK_PA4,
	TEGRA_PIN_DAP4_DOUT_PA5,
	TEGRA_PIN_DAP4_DIN_PA6,
	TEGRA_PIN_DAP4_FS_PA7,
	TEGRA_PIN_SOC_GPIO08_PB0,
	TEGRA_PIN_QSPI0_SCK_PC0,
	TEGRA_PIN_QSPI0_CS_N_PC1,
	TEGRA_PIN_QSPI0_IO0_PC2,
	TEGRA_PIN_QSPI0_IO1_PC3,
	TEGRA_PIN_QSPI0_IO2_PC4,
	TEGRA_PIN_QSPI0_IO3_PC5,
	TEGRA_PIN_QSPI1_SCK_PC6,
	TEGRA_PIN_QSPI1_CS_N_PC7,
	TEGRA_PIN_QSPI1_IO0_PD0,
	TEGRA_PIN_QSPI1_IO1_PD1,
	TEGRA_PIN_QSPI1_IO2_PD2,
	TEGRA_PIN_QSPI1_IO3_PD3,
	TEGRA_PIN_EQOS_TXC_PE0,
	TEGRA_PIN_EQOS_TD0_PE1,
	TEGRA_PIN_EQOS_TD1_PE2,
	TEGRA_PIN_EQOS_TD2_PE3,
	TEGRA_PIN_EQOS_TD3_PE4,
	TEGRA_PIN_EQOS_TX_CTL_PE5,
	TEGRA_PIN_EQOS_RD0_PE6,
	TEGRA_PIN_EQOS_RD1_PE7,
	TEGRA_PIN_EQOS_RD2_PF0,
	TEGRA_PIN_EQOS_RD3_PF1,
	TEGRA_PIN_EQOS_RX_CTL_PF2,
	TEGRA_PIN_EQOS_RXC_PF3,
	TEGRA_PIN_EQOS_SMA_MDIO_PF4,
	TEGRA_PIN_EQOS_SMA_MDC_PF5,
	TEGRA_PIN_SOC_GPIO13_PG0,
	TEGRA_PIN_SOC_GPIO14_PG1,
	TEGRA_PIN_SOC_GPIO15_PG2,
	TEGRA_PIN_SOC_GPIO16_PG3,
	TEGRA_PIN_SOC_GPIO17_PG4,
	TEGRA_PIN_SOC_GPIO18_PG5,
	TEGRA_PIN_SOC_GPIO19_PG6,
	TEGRA_PIN_SOC_GPIO20_PG7,
	TEGRA_PIN_SOC_GPIO21_PH0,
	TEGRA_PIN_SOC_GPIO22_PH1,
	TEGRA_PIN_SOC_GPIO06_PH2,
	TEGRA_PIN_UART4_TX_PH3,
	TEGRA_PIN_UART4_RX_PH4,
	TEGRA_PIN_UART4_RTS_PH5,
	TEGRA_PIN_UART4_CTS_PH6,
	TEGRA_PIN_SOC_GPIO41_PH7,
	TEGRA_PIN_SOC_GPIO42_PI0,
	TEGRA_PIN_SOC_GPIO43_PI1,
	TEGRA_PIN_SOC_GPIO44_PI2,
	TEGRA_PIN_GEN1_I2C_SCL_PI3,
	TEGRA_PIN_GEN1_I2C_SDA_PI4,
	TEGRA_PIN_CPU_PWR_REQ_PI5,
	TEGRA_PIN_SOC_GPIO07_PI6,
	TEGRA_PIN_SDMMC1_CLK_PJ0,
	TEGRA_PIN_SDMMC1_CMD_PJ1,
	TEGRA_PIN_SDMMC1_DAT0_PJ2,
	TEGRA_PIN_SDMMC1_DAT1_PJ3,
	TEGRA_PIN_SDMMC1_DAT2_PJ4,
	TEGRA_PIN_SDMMC1_DAT3_PJ5,
	TEGRA_PIN_PEX_L0_CLKREQ_N_PK0,
	TEGRA_PIN_PEX_L0_RST_N_PK1,
	TEGRA_PIN_PEX_L1_CLKREQ_N_PK2,
	TEGRA_PIN_PEX_L1_RST_N_PK3,
	TEGRA_PIN_PEX_L2_CLKREQ_N_PK4,
	TEGRA_PIN_PEX_L2_RST_N_PK5,
	TEGRA_PIN_PEX_L3_CLKREQ_N_PK6,

Annotation

Implementation Notes