drivers/pinctrl/tegra/pinctrl-tegra30.c

Source file repositories/reference/linux-study-clean/drivers/pinctrl/tegra/pinctrl-tegra30.c

File Facts

System
Linux kernel
Corpus path
drivers/pinctrl/tegra/pinctrl-tegra30.c
Extension
.c
Size
87561 bytes
Lines
2501
Domain
Driver Families
Bucket
drivers/pinctrl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Pinctrl data for the NVIDIA Tegra30 pinmux
 *
 * Author: Stephen Warren <swarren@nvidia.com>
 *
 * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
 */

#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#include "pinctrl-tegra.h"

/*
 * Most pins affected by the pinmux can also be GPIOs. Define these first.
 * These must match how the GPIO driver names/numbers its pins.
 */
#define _GPIO(offset)			(offset)

#define TEGRA_PIN_CLK_32K_OUT_PA0	_GPIO(0)
#define TEGRA_PIN_UART3_CTS_N_PA1	_GPIO(1)
#define TEGRA_PIN_DAP2_FS_PA2		_GPIO(2)
#define TEGRA_PIN_DAP2_SCLK_PA3		_GPIO(3)
#define TEGRA_PIN_DAP2_DIN_PA4		_GPIO(4)
#define TEGRA_PIN_DAP2_DOUT_PA5		_GPIO(5)
#define TEGRA_PIN_SDMMC3_CLK_PA6	_GPIO(6)
#define TEGRA_PIN_SDMMC3_CMD_PA7	_GPIO(7)
#define TEGRA_PIN_GMI_A17_PB0		_GPIO(8)
#define TEGRA_PIN_GMI_A18_PB1		_GPIO(9)
#define TEGRA_PIN_LCD_PWR0_PB2		_GPIO(10)
#define TEGRA_PIN_LCD_PCLK_PB3		_GPIO(11)
#define TEGRA_PIN_SDMMC3_DAT3_PB4	_GPIO(12)
#define TEGRA_PIN_SDMMC3_DAT2_PB5	_GPIO(13)
#define TEGRA_PIN_SDMMC3_DAT1_PB6	_GPIO(14)
#define TEGRA_PIN_SDMMC3_DAT0_PB7	_GPIO(15)
#define TEGRA_PIN_UART3_RTS_N_PC0	_GPIO(16)
#define TEGRA_PIN_LCD_PWR1_PC1		_GPIO(17)
#define TEGRA_PIN_UART2_TXD_PC2		_GPIO(18)
#define TEGRA_PIN_UART2_RXD_PC3		_GPIO(19)
#define TEGRA_PIN_GEN1_I2C_SCL_PC4	_GPIO(20)
#define TEGRA_PIN_GEN1_I2C_SDA_PC5	_GPIO(21)
#define TEGRA_PIN_LCD_PWR2_PC6		_GPIO(22)
#define TEGRA_PIN_GMI_WP_N_PC7		_GPIO(23)
#define TEGRA_PIN_SDMMC3_DAT5_PD0	_GPIO(24)
#define TEGRA_PIN_SDMMC3_DAT4_PD1	_GPIO(25)
#define TEGRA_PIN_LCD_DC1_PD2		_GPIO(26)
#define TEGRA_PIN_SDMMC3_DAT6_PD3	_GPIO(27)
#define TEGRA_PIN_SDMMC3_DAT7_PD4	_GPIO(28)
#define TEGRA_PIN_VI_D1_PD5		_GPIO(29)
#define TEGRA_PIN_VI_VSYNC_PD6		_GPIO(30)
#define TEGRA_PIN_VI_HSYNC_PD7		_GPIO(31)
#define TEGRA_PIN_LCD_D0_PE0		_GPIO(32)
#define TEGRA_PIN_LCD_D1_PE1		_GPIO(33)
#define TEGRA_PIN_LCD_D2_PE2		_GPIO(34)
#define TEGRA_PIN_LCD_D3_PE3		_GPIO(35)
#define TEGRA_PIN_LCD_D4_PE4		_GPIO(36)
#define TEGRA_PIN_LCD_D5_PE5		_GPIO(37)
#define TEGRA_PIN_LCD_D6_PE6		_GPIO(38)
#define TEGRA_PIN_LCD_D7_PE7		_GPIO(39)
#define TEGRA_PIN_LCD_D8_PF0		_GPIO(40)
#define TEGRA_PIN_LCD_D9_PF1		_GPIO(41)
#define TEGRA_PIN_LCD_D10_PF2		_GPIO(42)
#define TEGRA_PIN_LCD_D11_PF3		_GPIO(43)
#define TEGRA_PIN_LCD_D12_PF4		_GPIO(44)
#define TEGRA_PIN_LCD_D13_PF5		_GPIO(45)
#define TEGRA_PIN_LCD_D14_PF6		_GPIO(46)
#define TEGRA_PIN_LCD_D15_PF7		_GPIO(47)
#define TEGRA_PIN_GMI_AD0_PG0		_GPIO(48)
#define TEGRA_PIN_GMI_AD1_PG1		_GPIO(49)
#define TEGRA_PIN_GMI_AD2_PG2		_GPIO(50)
#define TEGRA_PIN_GMI_AD3_PG3		_GPIO(51)
#define TEGRA_PIN_GMI_AD4_PG4		_GPIO(52)
#define TEGRA_PIN_GMI_AD5_PG5		_GPIO(53)
#define TEGRA_PIN_GMI_AD6_PG6		_GPIO(54)
#define TEGRA_PIN_GMI_AD7_PG7		_GPIO(55)
#define TEGRA_PIN_GMI_AD8_PH0		_GPIO(56)
#define TEGRA_PIN_GMI_AD9_PH1		_GPIO(57)
#define TEGRA_PIN_GMI_AD10_PH2		_GPIO(58)
#define TEGRA_PIN_GMI_AD11_PH3		_GPIO(59)
#define TEGRA_PIN_GMI_AD12_PH4		_GPIO(60)
#define TEGRA_PIN_GMI_AD13_PH5		_GPIO(61)
#define TEGRA_PIN_GMI_AD14_PH6		_GPIO(62)
#define TEGRA_PIN_GMI_AD15_PH7		_GPIO(63)
#define TEGRA_PIN_GMI_WR_N_PI0		_GPIO(64)
#define TEGRA_PIN_GMI_OE_N_PI1		_GPIO(65)
#define TEGRA_PIN_GMI_DQS_PI2		_GPIO(66)

Annotation

Implementation Notes