drivers/pinctrl/vt8500/pinctrl-vt8500.c
Source file repositories/reference/linux-study-clean/drivers/pinctrl/vt8500/pinctrl-vt8500.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pinctrl/vt8500/pinctrl-vt8500.c- Extension
.c- Size
- 14787 bytes
- Lines
- 480
- Domain
- Driver Families
- Bucket
- drivers/pinctrl
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/io.hlinux/init.hlinux/pinctrl/pinctrl.hlinux/platform_device.hlinux/slab.hpinctrl-wmt.h
Detected Declarations
function vt8500_pinctrl_probe
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Pinctrl data for VIA VT8500 SoC
*
* Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
*/
#include <linux/io.h>
#include <linux/init.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "pinctrl-wmt.h"
/*
* Describe the register offsets within the GPIO memory space
* The dedicated external GPIO's should always be listed in bank 0
* so they are exported in the 0..31 range which is what users
* expect.
*
* Do not reorder these banks as it will change the pin numbering
*/
static const struct wmt_pinctrl_bank_registers vt8500_banks[] = {
WMT_PINCTRL_BANK(NO_REG, 0x3C, 0x5C, 0x7C, NO_REG, NO_REG), /* 0 */
WMT_PINCTRL_BANK(0x00, 0x20, 0x40, 0x60, NO_REG, NO_REG), /* 1 */
WMT_PINCTRL_BANK(0x04, 0x24, 0x44, 0x64, NO_REG, NO_REG), /* 2 */
WMT_PINCTRL_BANK(0x08, 0x28, 0x48, 0x68, NO_REG, NO_REG), /* 3 */
WMT_PINCTRL_BANK(0x0C, 0x2C, 0x4C, 0x6C, NO_REG, NO_REG), /* 4 */
WMT_PINCTRL_BANK(0x10, 0x30, 0x50, 0x70, NO_REG, NO_REG), /* 5 */
WMT_PINCTRL_BANK(0x14, 0x34, 0x54, 0x74, NO_REG, NO_REG), /* 6 */
};
/* Please keep sorted by bank/bit */
#define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0)
#define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1)
#define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2)
#define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3)
#define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4)
#define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5)
#define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6)
#define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7)
#define WMT_PIN_EXTGPIO8 WMT_PIN(0, 8)
#define WMT_PIN_UART0RTS WMT_PIN(1, 0)
#define WMT_PIN_UART0TXD WMT_PIN(1, 1)
#define WMT_PIN_UART0CTS WMT_PIN(1, 2)
#define WMT_PIN_UART0RXD WMT_PIN(1, 3)
#define WMT_PIN_UART1RTS WMT_PIN(1, 4)
#define WMT_PIN_UART1TXD WMT_PIN(1, 5)
#define WMT_PIN_UART1CTS WMT_PIN(1, 6)
#define WMT_PIN_UART1RXD WMT_PIN(1, 7)
#define WMT_PIN_SPI0CLK WMT_PIN(1, 8)
#define WMT_PIN_SPI0SS WMT_PIN(1, 9)
#define WMT_PIN_SPI0MISO WMT_PIN(1, 10)
#define WMT_PIN_SPI0MOSI WMT_PIN(1, 11)
#define WMT_PIN_SPI1CLK WMT_PIN(1, 12)
#define WMT_PIN_SPI1SS WMT_PIN(1, 13)
#define WMT_PIN_SPI1MISO WMT_PIN(1, 14)
#define WMT_PIN_SPI1MOSI WMT_PIN(1, 15)
#define WMT_PIN_SPI2CLK WMT_PIN(1, 16)
#define WMT_PIN_SPI2SS WMT_PIN(1, 17)
#define WMT_PIN_SPI2MISO WMT_PIN(1, 18)
#define WMT_PIN_SPI2MOSI WMT_PIN(1, 19)
#define WMT_PIN_SDDATA0 WMT_PIN(2, 0)
#define WMT_PIN_SDDATA1 WMT_PIN(2, 1)
#define WMT_PIN_SDDATA2 WMT_PIN(2, 2)
#define WMT_PIN_SDDATA3 WMT_PIN(2, 3)
#define WMT_PIN_MMCDATA0 WMT_PIN(2, 4)
#define WMT_PIN_MMCDATA1 WMT_PIN(2, 5)
#define WMT_PIN_MMCDATA2 WMT_PIN(2, 6)
#define WMT_PIN_MMCDATA3 WMT_PIN(2, 7)
#define WMT_PIN_SDCLK WMT_PIN(2, 8)
#define WMT_PIN_SDWP WMT_PIN(2, 9)
#define WMT_PIN_SDCMD WMT_PIN(2, 10)
#define WMT_PIN_MSDATA0 WMT_PIN(2, 16)
#define WMT_PIN_MSDATA1 WMT_PIN(2, 17)
#define WMT_PIN_MSDATA2 WMT_PIN(2, 18)
#define WMT_PIN_MSDATA3 WMT_PIN(2, 19)
#define WMT_PIN_MSCLK WMT_PIN(2, 20)
#define WMT_PIN_MSBS WMT_PIN(2, 21)
#define WMT_PIN_MSINS WMT_PIN(2, 22)
#define WMT_PIN_I2C0SCL WMT_PIN(2, 24)
#define WMT_PIN_I2C0SDA WMT_PIN(2, 25)
#define WMT_PIN_I2C1SCL WMT_PIN(2, 26)
#define WMT_PIN_I2C1SDA WMT_PIN(2, 27)
#define WMT_PIN_MII0RXD0 WMT_PIN(3, 0)
#define WMT_PIN_MII0RXD1 WMT_PIN(3, 1)
#define WMT_PIN_MII0RXD2 WMT_PIN(3, 2)
#define WMT_PIN_MII0RXD3 WMT_PIN(3, 3)
#define WMT_PIN_MII0RXCLK WMT_PIN(3, 4)
Annotation
- Immediate include surface: `linux/io.h`, `linux/init.h`, `linux/pinctrl/pinctrl.h`, `linux/platform_device.h`, `linux/slab.h`, `pinctrl-wmt.h`.
- Detected declarations: `function vt8500_pinctrl_probe`.
- Atlas domain: Driver Families / drivers/pinctrl.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.