drivers/platform/x86/intel/pmc/arl.c

Source file repositories/reference/linux-study-clean/drivers/platform/x86/intel/pmc/arl.c

File Facts

System
Linux kernel
Corpus path
drivers/platform/x86/intel/pmc/arl.c
Extension
.c
Size
22190 bytes
Lines
746
Domain
Driver Families
Bucket
drivers/platform
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * This file contains platform specific structure definitions
 * and init function used by Arrow Lake PCH.
 *
 * Copyright (c) 2022, Intel Corporation.
 * All Rights Reserved.
 *
 */

#include <linux/pci.h>
#include "core.h"

/* PMC SSRAM PMT Telemetry GUID */
#define IOEP_LPM_REQ_GUID	0x5077612
#define SOCS_LPM_REQ_GUID	0x8478657
#define PCHS_LPM_REQ_GUID	0x9684572
#define SOCM_LPM_REQ_GUID	0x2625030

static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};

static const struct pmc_bit_map arl_socs_ltr_show_map[] = {
	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
	{"SATA",		CNP_PMC_LTR_SATA},
	{"GIGABIT_ETHERNET",	CNP_PMC_LTR_GBE},
	{"XHCI",		CNP_PMC_LTR_XHCI},
	{"SOUTHPORT_F",		ADL_PMC_LTR_SPF},
	{"ME",			CNP_PMC_LTR_ME},
	/* EVA is Enterprise Value Add, doesn't really exist on PCH */
	{"SATA1",		CNP_PMC_LTR_EVA},
	{"SOUTHPORT_C",		CNP_PMC_LTR_SPC},
	{"HD_AUDIO",		CNP_PMC_LTR_AZ},
	{"CNV",			CNP_PMC_LTR_CNV},
	{"LPSS",		CNP_PMC_LTR_LPSS},
	{"SOUTHPORT_D",		CNP_PMC_LTR_SPD},
	{"SOUTHPORT_E",		CNP_PMC_LTR_SPE},
	{"SATA2",		CNP_PMC_LTR_CAM},
	{"ESPI",		CNP_PMC_LTR_ESPI},
	{"SCC",			CNP_PMC_LTR_SCC},
	{"ISH",			CNP_PMC_LTR_ISH},
	{"UFSX2",		CNP_PMC_LTR_UFSX2},
	{"EMMC",		CNP_PMC_LTR_EMMC},
	/*
	 * Check intel_pmc_core_ids[] users of cnp_reg_map for
	 * a list of core SoCs using this.
	 */
	{"WIGIG",		ICL_PMC_LTR_WIGIG},
	{"THC0",		TGL_PMC_LTR_THC0},
	{"THC1",		TGL_PMC_LTR_THC1},
	{"SOUTHPORT_G",		MTL_PMC_LTR_SPG},
	{"Reserved",		ARL_SOCS_PMC_LTR_RESERVED},
	{"IOE_PMC",		MTL_PMC_LTR_IOE_PMC},
	{"DMI3",		ARL_PMC_LTR_DMI3},

	/* Below two cannot be used for LTR_IGNORE */
	{"CURRENT_PLATFORM",	CNP_PMC_LTR_CUR_PLT},
	{"AGGREGATED_SYSTEM",	CNP_PMC_LTR_CUR_ASLT},
	{}
};

static const struct pmc_bit_map arl_socs_clocksource_status_map[] = {
	{"AON2_OFF_STS",		BIT(0)},
	{"AON3_OFF_STS",		BIT(1)},
	{"AON4_OFF_STS",		BIT(2)},
	{"AON5_OFF_STS",		BIT(3)},
	{"AON1_OFF_STS",		BIT(4)},
	{"XTAL_LVM_OFF_STS",		BIT(5)},
	{"AON3_SPL_OFF_STS",		BIT(9)},
	{"DMI3FPW_0_PLL_OFF_STS",	BIT(10)},
	{"DMI3FPW_1_PLL_OFF_STS",	BIT(11)},
	{"G5X16FPW_0_PLL_OFF_STS",	BIT(14)},
	{"G5X16FPW_1_PLL_OFF_STS",	BIT(15)},
	{"G5X16FPW_2_PLL_OFF_STS",	BIT(16)},
	{"XTAL_AGGR_OFF_STS",		BIT(17)},
	{"USB2_PLL_OFF_STS",		BIT(18)},
	{"G5X16FPW_3_PLL_OFF_STS",	BIT(19)},
	{"BCLK_EXT_INJ_CLK_OFF_STS",	BIT(20)},
	{"PHY_OC_EXT_INJ_CLK_OFF_STS",	BIT(21)},
	{"FILTER_PLL_OFF_STS",		BIT(22)},
	{"FABRIC_PLL_OFF_STS",		BIT(25)},
	{"SOC_PLL_OFF_STS",		BIT(26)},
	{"PCIEFAB_PLL_OFF_STS",		BIT(27)},
	{"REF_PLL_OFF_STS",		BIT(28)},
	{"GENLOCK_FILTER_PLL_OFF_STS",	BIT(30)},
	{"RTC_PLL_OFF_STS",		BIT(31)},
	{}
};

static const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = {

Annotation

Implementation Notes