drivers/platform/x86/intel/pmc/lnl.c

Source file repositories/reference/linux-study-clean/drivers/platform/x86/intel/pmc/lnl.c

File Facts

System
Linux kernel
Corpus path
drivers/platform/x86/intel/pmc/lnl.c
Extension
.c
Size
16745 bytes
Lines
583
Domain
Driver Families
Bucket
drivers/platform
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * This file contains platform specific structure definitions
 * and init function used by Lunar Lake PCH.
 *
 * Copyright (c) 2022, Intel Corporation.
 * All Rights Reserved.
 *
 */

#include <linux/cpu.h>
#include <linux/pci.h>

#include "core.h"

#define SOCM_LPM_REQ_GUID	0x15099748

static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};

static const struct pmc_bit_map lnl_ltr_show_map[] = {
	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
	{"SATA",		CNP_PMC_LTR_SATA},
	{"GIGABIT_ETHERNET",	CNP_PMC_LTR_GBE},
	{"XHCI",		CNP_PMC_LTR_XHCI},
	{"SOUTHPORT_F",		ADL_PMC_LTR_SPF},
	{"ME",			CNP_PMC_LTR_ME},
	/* EVA is Enterprise Value Add, doesn't really exist on PCH */
	{"SATA1",		CNP_PMC_LTR_EVA},
	{"SOUTHPORT_C",		CNP_PMC_LTR_SPC},
	{"HD_AUDIO",		CNP_PMC_LTR_AZ},
	{"CNV",			CNP_PMC_LTR_CNV},
	{"LPSS",		CNP_PMC_LTR_LPSS},
	{"SOUTHPORT_D",		CNP_PMC_LTR_SPD},
	{"SOUTHPORT_E",		CNP_PMC_LTR_SPE},
	{"SATA2",		CNP_PMC_LTR_CAM},
	{"ESPI",		CNP_PMC_LTR_ESPI},
	{"SCC",			CNP_PMC_LTR_SCC},
	{"ISH",			CNP_PMC_LTR_ISH},
	{"UFSX2",		CNP_PMC_LTR_UFSX2},
	{"EMMC",		CNP_PMC_LTR_EMMC},
	/*
	 * Check intel_pmc_core_ids[] users of cnp_reg_map for
	 * a list of core SoCs using this.
	 */
	{"WIGIG",		ICL_PMC_LTR_WIGIG},
	{"THC0",		TGL_PMC_LTR_THC0},
	{"THC1",		TGL_PMC_LTR_THC1},
	{"SOUTHPORT_G",		CNP_PMC_LTR_RESERVED},

	{"ESE",			MTL_PMC_LTR_ESE},
	{"IOE_PMC",		MTL_PMC_LTR_IOE_PMC},
	{"DMI3",		ARL_PMC_LTR_DMI3},
	{"OSSE",		LNL_PMC_LTR_OSSE},

	/* Below two cannot be used for LTR_IGNORE */
	{"CURRENT_PLATFORM",	CNP_PMC_LTR_CUR_PLT},
	{"AGGREGATED_SYSTEM",	CNP_PMC_LTR_CUR_ASLT},
	{}
};

static const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
	{"PMC_PGD0_PG_STS",			BIT(0),		0},
	{"FUSE_OSSE_PGD0_PG_STS",		BIT(1),		0},
	{"ESPISPI_PGD0_PG_STS",			BIT(2),		0},
	{"XHCI_PGD0_PG_STS",			BIT(3),		1},
	{"SPA_PGD0_PG_STS",			BIT(4),		1},
	{"SPB_PGD0_PG_STS",			BIT(5),		1},
	{"SPR16B0_PGD0_PG_STS",			BIT(6),		0},
	{"GBE_PGD0_PG_STS",			BIT(7),		1},
	{"SBR8B7_PGD0_PG_STS",			BIT(8),		0},
	{"SBR8B6_PGD0_PG_STS",			BIT(9),		0},
	{"SBR16B1_PGD0_PG_STS",			BIT(10),	0},
	{"SBR8B8_PGD0_PG_STS",			BIT(11),	0},
	{"ESE_PGD3_PG_STS",			BIT(12),	1},
	{"D2D_DISP_PGD0_PG_STS",		BIT(13),	1},
	{"LPSS_PGD0_PG_STS",			BIT(14),	1},
	{"LPC_PGD0_PG_STS",			BIT(15),	0},
	{"SMB_PGD0_PG_STS",			BIT(16),	0},
	{"ISH_PGD0_PG_STS",			BIT(17),	0},
	{"SBR8B2_PGD0_PG_STS",			BIT(18),	0},
	{"NPK_PGD0_PG_STS",			BIT(19),	0},
	{"D2D_NOC_PGD0_PG_STS",			BIT(20),	0},
	{"SAFSS_PGD0_PG_STS",			BIT(21),	0},
	{"FUSE_PGD0_PG_STS",			BIT(22),	0},
	{"D2D_DISP_PGD1_PG_STS",		BIT(23),	1},
	{"MPFPW1_PGD0_PG_STS",			BIT(24),	0},
	{"XDCI_PGD0_PG_STS",			BIT(25),	1},
	{"EXI_PGD0_PG_STS",			BIT(26),	0},
	{"CSE_PGD0_PG_STS",			BIT(27),	1},

Annotation

Implementation Notes