drivers/platform/x86/intel/pmc/mtl.c

Source file repositories/reference/linux-study-clean/drivers/platform/x86/intel/pmc/mtl.c

File Facts

System
Linux kernel
Corpus path
drivers/platform/x86/intel/pmc/mtl.c
Extension
.c
Size
33782 bytes
Lines
1007
Domain
Driver Families
Bucket
drivers/platform
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * This file contains platform specific structure definitions
 * and init function used by Meteor Lake PCH.
 *
 * Copyright (c) 2022, Intel Corporation.
 * All Rights Reserved.
 *
 */

#include <linux/pci.h>
#include "core.h"

/* PMC SSRAM PMT Telemetry GUIDS */
#define SOCP_LPM_REQ_GUID	0x2625030
#define IOEM_LPM_REQ_GUID	0x4357464
#define IOEP_LPM_REQ_GUID	0x5077612

static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};

/*
 * Die Mapping to Product.
 * Product SOCDie IOEDie PCHDie
 * MTL-M   SOC-M  IOE-M  None
 * MTL-P   SOC-M  IOE-P  None
 * MTL-S   SOC-S  IOE-P  PCH-S
 */

const struct pmc_bit_map mtl_socm_pfear_map[] = {
	{"PMC",                 BIT(0)},
	{"OPI",                 BIT(1)},
	{"SPI",                 BIT(2)},
	{"XHCI",                BIT(3)},
	{"SPA",                 BIT(4)},
	{"SPB",                 BIT(5)},
	{"SPC",                 BIT(6)},
	{"GBE",                 BIT(7)},

	{"SATA",                BIT(0)},
	{"DSP0",                BIT(1)},
	{"DSP1",                BIT(2)},
	{"DSP2",                BIT(3)},
	{"DSP3",                BIT(4)},
	{"SPD",                 BIT(5)},
	{"LPSS",                BIT(6)},
	{"LPC",                 BIT(7)},

	{"SMB",                 BIT(0)},
	{"ISH",                 BIT(1)},
	{"P2SB",                BIT(2)},
	{"NPK_VNN",             BIT(3)},
	{"SDX",                 BIT(4)},
	{"SPE",                 BIT(5)},
	{"FUSE",                BIT(6)},
	{"SBR8",                BIT(7)},

	{"RSVD24",              BIT(0)},
	{"OTG",                 BIT(1)},
	{"EXI",                 BIT(2)},
	{"CSE",                 BIT(3)},
	{"CSME_KVM",            BIT(4)},
	{"CSME_PMT",            BIT(5)},
	{"CSME_CLINK",          BIT(6)},
	{"CSME_PTIO",           BIT(7)},

	{"CSME_USBR",           BIT(0)},
	{"CSME_SUSRAM",         BIT(1)},
	{"CSME_SMT1",           BIT(2)},
	{"RSVD35",              BIT(3)},
	{"CSME_SMS2",           BIT(4)},
	{"CSME_SMS",            BIT(5)},
	{"CSME_RTC",            BIT(6)},
	{"CSME_PSF",            BIT(7)},

	{"SBR0",                BIT(0)},
	{"SBR1",                BIT(1)},
	{"SBR2",                BIT(2)},
	{"SBR3",                BIT(3)},
	{"SBR4",                BIT(4)},
	{"SBR5",                BIT(5)},
	{"RSVD46",              BIT(6)},
	{"PSF1",                BIT(7)},

	{"PSF2",                BIT(0)},
	{"PSF3",                BIT(1)},
	{"PSF4",                BIT(2)},
	{"CNVI",                BIT(3)},
	{"UFSX2",               BIT(4)},
	{"EMMC",                BIT(5)},
	{"SPF",                 BIT(6)},

Annotation

Implementation Notes