drivers/platform/x86/intel/pmc/wcl.c

Source file repositories/reference/linux-study-clean/drivers/platform/x86/intel/pmc/wcl.c

File Facts

System
Linux kernel
Corpus path
drivers/platform/x86/intel/pmc/wcl.c
Extension
.c
Size
17201 bytes
Lines
505
Domain
Driver Families
Bucket
drivers/platform
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * This file contains platform specific structure definitions
 * and init function used by Wildcat Lake PCH.
 *
 * Copyright (c) 2025, Intel Corporation.
 */

#include <linux/bits.h>
#include <linux/pci.h>

#include "core.h"

/* PMC SSRAM PMT Telemetry GUIDS */
#define PCDN_LPM_REQ_GUID 0x33747648

static const struct pmc_bit_map wcl_pcdn_pfear_map[] = {
	{"PMC_0",               BIT(0)},
	{"FUSE_OSSE",           BIT(1)},
	{"ESPISPI",             BIT(2)},
	{"XHCI",                BIT(3)},
	{"SPA",                 BIT(4)},
	{"RSVD",                BIT(5)},
	{"MPFPW2",              BIT(6)},
	{"GBE",                 BIT(7)},

	{"SBR16B21",            BIT(0)},
	{"SBR16B5",             BIT(1)},
	{"SBR8B1",              BIT(2)},
	{"SBR8B0",              BIT(3)},
	{"P2SB0",               BIT(4)},
	{"D2D_DISP_1",          BIT(5)},
	{"LPSS",                BIT(6)},
	{"LPC",                 BIT(7)},

	{"SMB",                 BIT(0)},
	{"ISH",                 BIT(1)},
	{"DBG_SBR16B",          BIT(2)},
	{"NPK_0",               BIT(3)},
	{"D2D_NOC_1",           BIT(4)},
	{"FIA_P",               BIT(5)},
	{"FUSE",                BIT(6)},
	{"DBG_PSF",             BIT(7)},

	{"DISP_PGA1",           BIT(0)},
	{"XDCI",                BIT(1)},
	{"EXI",                 BIT(2)},
	{"CSE",                 BIT(3)},
	{"KVMCC",               BIT(4)},
	{"PMT",                 BIT(5)},
	{"CLINK",               BIT(6)},
	{"PTIO",                BIT(7)},

	{"USBR0",               BIT(0)},
	{"SBR16B22",            BIT(1)},
	{"SMT1",                BIT(2)},
	{"MPFPW1",              BIT(3)},
	{"SMS2",                BIT(4)},
	{"SMS1",                BIT(5)},
	{"CSMERTC",             BIT(6)},
	{"CSMEPSF",             BIT(7)},

	{"D2D_NOC_0",           BIT(0)},
	{"ESE",                 BIT(1)},
	{"FIACPCB_P",           BIT(2)},
	{"RSVD",                BIT(3)},
	{"SBR8B2",              BIT(4)},
	{"OSSE_SMT1",           BIT(5)},
	{"D2D_DISP",            BIT(6)},
	{"P2SB1",               BIT(7)},

	{"U3FPW1",              BIT(0)},
	{"SBR16B3",             BIT(1)},
	{"PSF4",                BIT(2)},
	{"CNVI",                BIT(3)},
	{"UFSX2",               BIT(4)},
	{"ENDBG",               BIT(5)},
	{"DBC",                 BIT(6)},
	{"SBRG",                BIT(7)},

	{"RSVD",                BIT(0)},
	{"NPK1",                BIT(1)},
	{"SBR16B7",             BIT(2)},
	{"SBR16B4",             BIT(3)},
	{"FIA_XG",              BIT(4)},
	{"PSF6",                BIT(5)},
	{"UFSPW1",              BIT(6)},
	{"FIA_U",               BIT(7)},

	{"PSF8",                BIT(0)},

Annotation

Implementation Notes