drivers/pmdomain/amlogic/meson-ee-pwrc.c

Source file repositories/reference/linux-study-clean/drivers/pmdomain/amlogic/meson-ee-pwrc.c

File Facts

System
Linux kernel
Corpus path
drivers/pmdomain/amlogic/meson-ee-pwrc.c
Extension
.c
Size
19314 bytes
Lines
653
Domain
Driver Families
Bucket
drivers/pmdomain
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct meson_ee_pwrc_mem_domain {
	unsigned int reg;
	unsigned int mask;
};

struct meson_ee_pwrc_top_domain {
	unsigned int sleep_reg;
	unsigned int sleep_mask;
	unsigned int iso_reg;
	unsigned int iso_mask;
};

struct meson_ee_pwrc_domain_desc {
	char *name;
	unsigned int reset_names_count;
	unsigned int clk_names_count;
	const struct meson_ee_pwrc_top_domain *top_pd;
	unsigned int mem_pd_count;
	const struct meson_ee_pwrc_mem_domain *mem_pd;
	bool (*is_powered_off)(struct meson_ee_pwrc_domain *pwrc_domain);
};

struct meson_ee_pwrc_domain_data {
	unsigned int count;
	const struct meson_ee_pwrc_domain_desc *domains;
};

/* TOP Power Domains */

static const struct meson_ee_pwrc_top_domain gx_pwrc_vpu = {
	.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
	.sleep_mask = BIT(8),
	.iso_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
	.iso_mask = BIT(9),
};

static const struct meson_ee_pwrc_top_domain meson8_pwrc_vpu = {
	.sleep_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
	.sleep_mask = BIT(8),
	.iso_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
	.iso_mask = BIT(9),
};

#define SM1_EE_PD(__bit)					\
	{							\
		.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 		\
		.sleep_mask = BIT(__bit), 			\
		.iso_reg = GX_AO_RTI_GEN_PWR_ISO0, 		\
		.iso_mask = BIT(__bit), 			\
	}

static const struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
static const struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
static const struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
static const struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
static const struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);

static const struct meson_ee_pwrc_top_domain g12a_pwrc_nna = {
	.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
	.sleep_mask = BIT(16) | BIT(17),
	.iso_reg = GX_AO_RTI_GEN_PWR_ISO0,
	.iso_mask = BIT(16) | BIT(17),
};

static const struct meson_ee_pwrc_top_domain g12a_pwrc_isp = {
	.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
	.sleep_mask = BIT(18) | BIT(19),
	.iso_reg = GX_AO_RTI_GEN_PWR_ISO0,
	.iso_mask = BIT(18) | BIT(19),
};

/* Memory PD Domains */

#define VPU_MEMPD(__reg)					\
	{ __reg, GENMASK(1, 0) },				\
	{ __reg, GENMASK(3, 2) },				\
	{ __reg, GENMASK(5, 4) },				\
	{ __reg, GENMASK(7, 6) },				\
	{ __reg, GENMASK(9, 8) },				\
	{ __reg, GENMASK(11, 10) },				\
	{ __reg, GENMASK(13, 12) },				\
	{ __reg, GENMASK(15, 14) },				\
	{ __reg, GENMASK(17, 16) },				\
	{ __reg, GENMASK(19, 18) },				\
	{ __reg, GENMASK(21, 20) },				\
	{ __reg, GENMASK(23, 22) },				\
	{ __reg, GENMASK(25, 24) },				\
	{ __reg, GENMASK(27, 26) },				\
	{ __reg, GENMASK(29, 28) },				\
	{ __reg, GENMASK(31, 30) }

Annotation

Implementation Notes