drivers/pmdomain/mediatek/mt8183-pm-domains.h

Source file repositories/reference/linux-study-clean/drivers/pmdomain/mediatek/mt8183-pm-domains.h

File Facts

System
Linux kernel
Corpus path
drivers/pmdomain/mediatek/mt8183-pm-domains.h
Extension
.h
Size
8700 bytes
Lines
301
Domain
Driver Families
Bucket
drivers/pmdomain
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H

#include "mtk-pm-domains.h"
#include <dt-bindings/power/mt8183-power.h>

/*
 * MT8183 power domain support
 */
static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8183[] = {
	BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI
};

static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
	[MT8183_POWER_DOMAIN_AUDIO] = {
		.name = "audio",
		.sta_mask = PWR_STATUS_AUDIO,
		.ctl_offs = 0x0314,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
	},
	[MT8183_POWER_DOMAIN_CONN] = {
		.name = "conn",
		.sta_mask = PWR_STATUS_CONN,
		.ctl_offs = 0x032c,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = 0,
		.sram_pdn_ack_bits = 0,
		.bp_cfg = {
			BUS_PROT_WR(INFRA,
				    MT8183_TOP_AXI_PROT_EN_CONN,
				    MT8183_TOP_AXI_PROT_EN_SET,
				    MT8183_TOP_AXI_PROT_EN_CLR,
				    MT8183_TOP_AXI_PROT_EN_STA1),
		},
	},
	[MT8183_POWER_DOMAIN_MFG_ASYNC] = {
		.name = "mfg_async",
		.sta_mask = PWR_STATUS_MFG_ASYNC,
		.ctl_offs = 0x0334,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = 0,
		.sram_pdn_ack_bits = 0,
		.caps = MTK_SCPD_DOMAIN_SUPPLY,
	},
	[MT8183_POWER_DOMAIN_MFG] = {
		.name = "mfg",
		.sta_mask = PWR_STATUS_MFG,
		.ctl_offs = 0x0338,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = GENMASK(8, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
		.caps = MTK_SCPD_DOMAIN_SUPPLY,
	},
	[MT8183_POWER_DOMAIN_MFG_CORE0] = {
		.name = "mfg_core0",
		.sta_mask = BIT(7),
		.ctl_offs = 0x034c,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = GENMASK(8, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
	},
	[MT8183_POWER_DOMAIN_MFG_CORE1] = {
		.name = "mfg_core1",
		.sta_mask = BIT(20),
		.ctl_offs = 0x0310,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = GENMASK(8, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
	},
	[MT8183_POWER_DOMAIN_MFG_2D] = {
		.name = "mfg_2d",
		.sta_mask = PWR_STATUS_MFG_2D,
		.ctl_offs = 0x0348,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = GENMASK(8, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
		.bp_cfg = {
			BUS_PROT_WR(INFRA,
				    MT8183_TOP_AXI_PROT_EN_1_MFG,
				    MT8183_TOP_AXI_PROT_EN_1_SET,
				    MT8183_TOP_AXI_PROT_EN_1_CLR,

Annotation

Implementation Notes