drivers/pmdomain/mediatek/mt8188-pm-domains.h

Source file repositories/reference/linux-study-clean/drivers/pmdomain/mediatek/mt8188-pm-domains.h

File Facts

System
Linux kernel
Corpus path
drivers/pmdomain/mediatek/mt8188-pm-domains.h
Extension
.h
Size
21051 bytes
Lines
697
Domain
Driver Families
Bucket
drivers/pmdomain
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H

#include "mtk-pm-domains.h"
#include <dt-bindings/power/mediatek,mt8188-power.h>

/*
 * MT8188 power domain support
 */

static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8188[] = {
	BUS_PROT_BLOCK_INFRA
};

static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
	[MT8188_POWER_DOMAIN_MFG0] = {
		.name = "mfg0",
		.sta_mask = BIT(1),
		.ctl_offs = 0x300,
		.pwr_sta_offs = 0x174,
		.pwr_sta2nd_offs = 0x178,
		.sram_pdn_bits = BIT(8),
		.sram_pdn_ack_bits = BIT(12),
		.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
	},
	[MT8188_POWER_DOMAIN_MFG1] = {
		.name = "mfg1",
		.sta_mask = BIT(2),
		.ctl_offs = 0x304,
		.pwr_sta_offs = 0x174,
		.pwr_sta2nd_offs = 0x178,
		.sram_pdn_bits = BIT(8),
		.sram_pdn_ack_bits = BIT(12),
		.bp_cfg = {
			BUS_PROT_WR(INFRA,
				    MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
				    MT8188_TOP_AXI_PROT_EN_SET,
				    MT8188_TOP_AXI_PROT_EN_CLR,
				    MT8188_TOP_AXI_PROT_EN_STA),
			BUS_PROT_WR(INFRA,
				    MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
				    MT8188_TOP_AXI_PROT_EN_2_SET,
				    MT8188_TOP_AXI_PROT_EN_2_CLR,
				    MT8188_TOP_AXI_PROT_EN_2_STA),
			BUS_PROT_WR(INFRA,
				    MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
				    MT8188_TOP_AXI_PROT_EN_1_SET,
				    MT8188_TOP_AXI_PROT_EN_1_CLR,
				    MT8188_TOP_AXI_PROT_EN_1_STA),
			BUS_PROT_WR(INFRA,
				    MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
				    MT8188_TOP_AXI_PROT_EN_2_SET,
				    MT8188_TOP_AXI_PROT_EN_2_CLR,
				    MT8188_TOP_AXI_PROT_EN_2_STA),
			BUS_PROT_WR(INFRA,
				    MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
				    MT8188_TOP_AXI_PROT_EN_SET,
				    MT8188_TOP_AXI_PROT_EN_CLR,
				    MT8188_TOP_AXI_PROT_EN_STA),
			BUS_PROT_WR(INFRA,
				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
		},
		.caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
	},
	[MT8188_POWER_DOMAIN_MFG2] = {
		.name = "mfg2",
		.sta_mask = BIT(3),
		.ctl_offs = 0x308,
		.pwr_sta_offs = 0x174,
		.pwr_sta2nd_offs = 0x178,
		.sram_pdn_bits = BIT(8),
		.sram_pdn_ack_bits = BIT(12),
		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
	},
	[MT8188_POWER_DOMAIN_MFG3] = {
		.name = "mfg3",
		.sta_mask = BIT(4),
		.ctl_offs = 0x30C,
		.pwr_sta_offs = 0x174,
		.pwr_sta2nd_offs = 0x178,
		.sram_pdn_bits = BIT(8),
		.sram_pdn_ack_bits = BIT(12),
		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
	},
	[MT8188_POWER_DOMAIN_MFG4] = {
		.name = "mfg4",
		.sta_mask = BIT(5),

Annotation

Implementation Notes