drivers/pmdomain/mediatek/mt8189-pm-domains.h
Source file repositories/reference/linux-study-clean/drivers/pmdomain/mediatek/mt8189-pm-domains.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/pmdomain/mediatek/mt8189-pm-domains.h- Extension
.h- Size
- 15703 bytes
- Lines
- 486
- Domain
- Driver Families
- Bucket
- drivers/pmdomain
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
mtk-pm-domains.hdt-bindings/power/mediatek,mt8189-power.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __SOC_MEDIATEK_MT8189_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8189_PM_DOMAINS_H
#include "mtk-pm-domains.h"
#include <dt-bindings/power/mediatek,mt8189-power.h>
/*
* MT8189 power domain support
*/
#define MT8189_SPM_PWR_STATUS 0x0f40
#define MT8189_SPM_PWR_STATUS_2ND 0x0f44
#define MT8189_SPM_PWR_STATUS_MSB 0x0f48
#define MT8189_SPM_PWR_STATUS_MSB_2ND 0x0f4c
#define MT8189_SPM_XPU_PWR_STATUS 0x0f50
#define MT8189_SPM_XPU_PWR_STATUS_2ND 0x0f54
#define MT8189_PROT_EN_EMICFG_GALS_SLP_SET 0x0084
#define MT8189_PROT_EN_EMICFG_GALS_SLP_CLR 0x0088
#define MT8189_PROT_EN_EMICFG_GALS_SLP_RDY 0x008c
#define MT8189_PROT_EN_MMSYS_STA_0_SET 0x0c14
#define MT8189_PROT_EN_MMSYS_STA_0_CLR 0x0c18
#define MT8189_PROT_EN_MMSYS_STA_0_RDY 0x0c1c
#define MT8189_PROT_EN_MMSYS_STA_1_SET 0x0c24
#define MT8189_PROT_EN_MMSYS_STA_1_CLR 0x0c28
#define MT8189_PROT_EN_MMSYS_STA_1_RDY 0x0c2c
#define MT8189_PROT_EN_INFRASYS_STA_0_SET 0x0c44
#define MT8189_PROT_EN_INFRASYS_STA_0_CLR 0x0c48
#define MT8189_PROT_EN_INFRASYS_STA_0_RDY 0x0c4c
#define MT8189_PROT_EN_INFRASYS_STA_1_SET 0x0c54
#define MT8189_PROT_EN_INFRASYS_STA_1_CLR 0x0c58
#define MT8189_PROT_EN_INFRASYS_STA_1_RDY 0x0c5c
#define MT8189_PROT_EN_PERISYS_STA_0_SET 0x0c84
#define MT8189_PROT_EN_PERISYS_STA_0_CLR 0x0c88
#define MT8189_PROT_EN_PERISYS_STA_0_RDY 0x0c8c
#define MT8189_PROT_EN_MCU_STA_0_SET 0x0c94
#define MT8189_PROT_EN_MCU_STA_0_CLR 0x0c98
#define MT8189_PROT_EN_MCU_STA_0_RDY 0x0c9c
#define MT8189_PROT_EN_MD_STA_0_SET 0x0ca4
#define MT8189_PROT_EN_MD_STA_0_CLR 0x0ca8
#define MT8189_PROT_EN_MD_STA_0_RDY 0x0cac
#define MT8189_PROT_EN_EMISYS_STA_0_MM_INFRA (GENMASK(21, 20))
#define MT8189_PROT_EN_INFRASYS_STA_0_CONN (BIT(8))
#define MT8189_PROT_EN_INFRASYS_STA_1_CONN (BIT(12))
#define MT8189_PROT_EN_INFRASYS_STA_0_MM_INFRA (BIT(16))
#define MT8189_PROT_EN_INFRASYS_STA_1_MM_INFRA (BIT(11))
#define MT8189_PROT_EN_INFRASYS_STA_1_MFG1 (BIT(20))
#define MT8189_PROT_EN_MCU_STA_0_CONN (BIT(1))
#define MT8189_PROT_EN_MCU_STA_0_CONN_2ND (BIT(0))
#define MT8189_PROT_EN_MD_STA_0_MFG1 (BIT(0) | BIT(2))
#define MT8189_PROT_EN_MD_STA_0_MFG1_2ND (BIT(4))
#define MT8189_PROT_EN_MM_INFRA_IGN (BIT(1))
#define MT8189_PROT_EN_MM_INFRA_2_IGN (BIT(0))
#define MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN (GENMASK(31, 30))
#define MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN (GENMASK(10, 9))
#define MT8189_PROT_EN_MMSYS_STA_0_DISP (GENMASK(1, 0))
#define MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1 (BIT(3))
#define MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1 (BIT(7))
#define MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE (BIT(2))
#define MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE (BIT(8))
#define MT8189_PROT_EN_MMSYS_STA_0_MDP0 (BIT(18))
#define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA (GENMASK(3, 2))
#define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND (GENMASK(15, 7))
#define MT8189_PROT_EN_MMSYS_STA_0_VDE0 (BIT(20))
#define MT8189_PROT_EN_MMSYS_STA_1_VDE0 (BIT(13))
#define MT8189_PROT_EN_MMSYS_STA_0_VEN0 (BIT(12))
#define MT8189_PROT_EN_MMSYS_STA_1_VEN0 (BIT(12))
#define MT8189_PROT_EN_PERISYS_STA_0_AUDIO (BIT(6))
#define MT8189_PROT_EN_PERISYS_STA_0_SSUSB (BIT(7))
#define MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1 (GENMASK(5, 4))
static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8189[] = {
BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI
};
static const struct scpsys_domain_data scpsys_domain_data_mt8189[] = {
[MT8189_POWER_DOMAIN_CONN] = {
.name = "conn",
.sta_mask = BIT(1),
.ctl_offs = 0xe04,
.pwr_sta_offs = MT8189_SPM_PWR_STATUS,
.pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND,
.bp_cfg = {
BUS_PROT_WR_IGN(INFRA,
MT8189_PROT_EN_MCU_STA_0_CONN,
MT8189_PROT_EN_MCU_STA_0_SET,
MT8189_PROT_EN_MCU_STA_0_CLR,
MT8189_PROT_EN_MCU_STA_0_RDY),
BUS_PROT_WR_IGN(INFRA,
Annotation
- Immediate include surface: `mtk-pm-domains.h`, `dt-bindings/power/mediatek,mt8189-power.h`.
- Atlas domain: Driver Families / drivers/pmdomain.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.