drivers/pmdomain/mediatek/mt8196-pm-domains.h

Source file repositories/reference/linux-study-clean/drivers/pmdomain/mediatek/mt8196-pm-domains.h

File Facts

System
Linux kernel
Corpus path
drivers/pmdomain/mediatek/mt8196-pm-domains.h
Extension
.h
Size
16422 bytes
Lines
626
Domain
Driver Families
Bucket
drivers/pmdomain
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SOC_MEDIATEK_MT8196_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8196_PM_DOMAINS_H

#include "mtk-pm-domains.h"
#include <dt-bindings/power/mediatek,mt8196-power.h>

/*
 * MT8196 and MT6991 power domain support
 */

/* INFRA TOP_AXI registers */
#define MT8196_TOP_AXI_PROT_EN_SET		0x4
#define MT8196_TOP_AXI_PROT_EN_CLR		0x8
#define MT8196_TOP_AXI_PROT_EN_STA		0xc
 #define MT8196_TOP_AXI_PROT_EN_SLEEP0_MD	BIT(29)

#define MT8196_TOP_AXI_PROT_EN_1_SET		0x24
#define MT8196_TOP_AXI_PROT_EN_1_CLR		0x28
#define MT8196_TOP_AXI_PROT_EN_1_STA		0x2c
 #define MT8196_TOP_AXI_PROT_EN_1_SLEEP1_MD	BIT(0)

/* SPM BUS_PROTECT registers */
#define MT8196_SPM_BUS_PROTECT_CON_SET		0xdc
#define MT8196_SPM_BUS_PROTECT_CON_CLR		0xe0
#define MT8196_SPM_BUS_PROTECT_RDY		0x208
 #define MT8196_SPM_PROT_EN_BUS_CONN		BIT(1)
 #define MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0	BIT(6)
 #define MT8196_SPM_PROT_EN_BUS_SSUSB_P0	BIT(7)
 #define MT8196_SPM_PROT_EN_BUS_SSUSB_P1	BIT(8)
 #define MT8196_SPM_PROT_EN_BUS_SSUSB_P23	BIT(9)
 #define MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2	BIT(10)
 #define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0	BIT(13)
 #define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1	BIT(14)
 #define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2	BIT(15)
 #define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0	BIT(16)
 #define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1	BIT(17)
 #define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2	BIT(18)
 #define MT8196_SPM_PROT_EN_BUS_AUDIO		BIT(19)
 #define MT8196_SPM_PROT_EN_BUS_ADSP_TOP	BIT(21)
 #define MT8196_SPM_PROT_EN_BUS_ADSP_INFRA	BIT(22)
 #define MT8196_SPM_PROT_EN_BUS_ADSP_AO		BIT(23)
 #define MT8196_SPM_PROT_EN_BUS_MM_PROC		BIT(24)

/* PWR_CON registers */
#define MT8196_PWR_ACK				BIT(30)
#define MT8196_PWR_ACK_2ND			BIT(31)

static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8196[] = {
	BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SPM
};

static const struct scpsys_domain_data scpsys_domain_data_mt8196[] = {
	[MT8196_POWER_DOMAIN_MD] = {
		.name = "md",
		.sta_mask = MT8196_PWR_ACK,
		.sta2nd_mask = MT8196_PWR_ACK_2ND,
		.ctl_offs = 0xe00,
		.pwr_sta_offs = 0xe00,
		.pwr_sta2nd_offs = 0xe00,
		.ext_buck_iso_offs = 0xefc,
		.ext_buck_iso_mask = GENMASK(1, 0),
		.bp_cfg = {
			BUS_PROT_WR_IGN(INFRA, MT8196_TOP_AXI_PROT_EN_SLEEP0_MD,
					MT8196_TOP_AXI_PROT_EN_SET,
					MT8196_TOP_AXI_PROT_EN_CLR,
					MT8196_TOP_AXI_PROT_EN_STA),
			BUS_PROT_WR_IGN(INFRA, MT8196_TOP_AXI_PROT_EN_1_SLEEP1_MD,
					MT8196_TOP_AXI_PROT_EN_1_SET,
					MT8196_TOP_AXI_PROT_EN_1_CLR,
					MT8196_TOP_AXI_PROT_EN_1_STA),
		},
		.caps = MTK_SCPD_MODEM_PWRSEQ | MTK_SCPD_EXT_BUCK_ISO |
			MTK_SCPD_SKIP_RESET_B | MTK_SCPD_KEEP_DEFAULT_OFF,
	},
	[MT8196_POWER_DOMAIN_CONN] = {
		.name = "conn",
		.sta_mask = MT8196_PWR_ACK,
		.sta2nd_mask = MT8196_PWR_ACK_2ND,
		.ctl_offs = 0xe04,
		.pwr_sta_offs = 0xe04,
		.pwr_sta2nd_offs = 0xe04,
		.bp_cfg = {
			BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_CONN,
					MT8196_SPM_BUS_PROTECT_CON_SET,
					MT8196_SPM_BUS_PROTECT_CON_CLR,
					MT8196_SPM_BUS_PROTECT_RDY),
		},
		.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
		.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
	},

Annotation

Implementation Notes