drivers/pmdomain/mediatek/mt8365-pm-domains.h

Source file repositories/reference/linux-study-clean/drivers/pmdomain/mediatek/mt8365-pm-domains.h

File Facts

System
Linux kernel
Corpus path
drivers/pmdomain/mediatek/mt8365-pm-domains.h
Extension
.h
Size
6261 bytes
Lines
202
Domain
Driver Families
Bucket
drivers/pmdomain
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H
#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H

#include "mtk-pm-domains.h"
#include <dt-bindings/power/mediatek,mt8365-power.h>

/*
 * MT8365 power domain support
 */

#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask)				\
		BUS_PROT_WR(INFRA, _mask,				\
			    MT8365_INFRA_TOPAXI_PROTECTEN_SET,		\
			    MT8365_INFRA_TOPAXI_PROTECTEN_CLR,		\
			    MT8365_INFRA_TOPAXI_PROTECTEN_STA1)

#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask)			\
		BUS_PROT_WR(INFRA, _mask,				\
			    MT8365_INFRA_TOPAXI_PROTECTEN_1_SET,	\
			    MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR,	\
			    MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)

#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port)			\
		BUS_PROT_WR(SMI, BIT(port),				\
			    MT8365_SMI_COMMON_CLAMP_EN_SET,		\
			    MT8365_SMI_COMMON_CLAMP_EN_CLR,		\
			    MT8365_SMI_COMMON_CLAMP_EN)

#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta)	\
		_BUS_PROT_STA(INFRA, INFRA_NAO, _set_mask, _set, _set,	\
			      _sta_mask, _sta,				\
			      BUS_PROT_INVERTED | BUS_PROT_REG_UPDATE)

static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8365[] = {
	BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_INFRA_NAO, BUS_PROT_BLOCK_SMI
};

static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {
	[MT8365_POWER_DOMAIN_MM] = {
		.name = "mm",
		.sta_mask = PWR_STATUS_DISP,
		.ctl_offs = 0x30c,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = GENMASK(8, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
		.bp_cfg = {
			MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
				MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
				MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
			MT8365_BUS_PROT_INFRA_WR_TOPAXI(
				MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
				MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
				MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
				MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
			MT8365_BUS_PROT_WAY_EN(
				MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
				MT8365_INFRA_TOPAXI_SI0_CTL,
				MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
				MT8365_INFRA_NAO_TOPAXI_SI0_STA),
			MT8365_BUS_PROT_WAY_EN(
				MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
				MT8365_INFRA_TOPAXI_SI2_CTL,
				MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
				MT8365_INFRA_NAO_TOPAXI_SI2_STA),
			MT8365_BUS_PROT_INFRA_WR_TOPAXI(
				MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
		},
		.caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,
	},
	[MT8365_POWER_DOMAIN_VENC] = {
		.name = "venc",
		.sta_mask = PWR_STATUS_VENC,
		.ctl_offs = 0x0304,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = GENMASK(8, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
		.bp_cfg = {
			MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
		},
	},
	[MT8365_POWER_DOMAIN_AUDIO] = {
		.name = "audio",
		.sta_mask = PWR_STATUS_AUDIO,
		.ctl_offs = 0x0314,
		.pwr_sta_offs = 0x0180,
		.pwr_sta2nd_offs = 0x0184,
		.sram_pdn_bits = GENMASK(12, 8),
		.sram_pdn_ack_bits = GENMASK(17, 13),

Annotation

Implementation Notes