drivers/pwm/pwm-axi-pwmgen.c

Source file repositories/reference/linux-study-clean/drivers/pwm/pwm-axi-pwmgen.c

File Facts

System
Linux kernel
Corpus path
drivers/pwm/pwm-axi-pwmgen.c
Extension
.c
Size
10188 bytes
Lines
342
Domain
Driver Families
Bucket
drivers/pwm
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct axi_pwmgen_ddata {
	struct regmap *regmap;
	unsigned long clk_rate_hz;
};

static const struct regmap_config axi_pwmgen_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = 0xFC,
};

/* This represents a hardware configuration for one channel */
struct axi_pwmgen_waveform {
	u32 period_cnt;
	u32 duty_cycle_cnt;
	u32 duty_offset_cnt;
};

static struct axi_pwmgen_ddata *axi_pwmgen_ddata_from_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static int axi_pwmgen_round_waveform_tohw(struct pwm_chip *chip,
					  struct pwm_device *pwm,
					  const struct pwm_waveform *wf,
					  void *_wfhw)
{
	struct axi_pwmgen_waveform *wfhw = _wfhw;
	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);
	int ret = 0;

	if (wf->period_length_ns == 0) {
		*wfhw = (struct axi_pwmgen_waveform){
			.period_cnt = 0,
			.duty_cycle_cnt = 0,
			.duty_offset_cnt = 0,
		};
	} else {
		/* With ddata->clk_rate_hz < NSEC_PER_SEC this won't overflow. */
		wfhw->period_cnt = min_t(u64,
					 mul_u64_u32_div(wf->period_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
					 U32_MAX);

		if (wfhw->period_cnt == 0) {
			/*
			 * The specified period is too short for the hardware.
			 * So round up .period_cnt to 1 (i.e. the smallest
			 * possible period). With .duty_cycle and .duty_offset
			 * being less than or equal to .period, their rounded
			 * value must be 0.
			 */
			wfhw->period_cnt = 1;
			wfhw->duty_cycle_cnt = 0;
			wfhw->duty_offset_cnt = 0;
			ret = 1;
		} else {
			wfhw->duty_cycle_cnt = min_t(u64,
						     mul_u64_u32_div(wf->duty_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
						     U32_MAX);
			wfhw->duty_offset_cnt = min_t(u64,
						      mul_u64_u32_div(wf->duty_offset_ns, ddata->clk_rate_hz, NSEC_PER_SEC),
						      U32_MAX);
		}
	}

	dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> PERIOD: %08x, DUTY: %08x, OFFSET: %08x\n",
		pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,
		ddata->clk_rate_hz, wfhw->period_cnt, wfhw->duty_cycle_cnt, wfhw->duty_offset_cnt);

	return ret;
}

static int axi_pwmgen_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm,
					     const void *_wfhw, struct pwm_waveform *wf)
{
	const struct axi_pwmgen_waveform *wfhw = _wfhw;
	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);

	wf->period_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->period_cnt * NSEC_PER_SEC,
					ddata->clk_rate_hz);

	wf->duty_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_cycle_cnt * NSEC_PER_SEC,
					    ddata->clk_rate_hz);

	wf->duty_offset_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_offset_cnt * NSEC_PER_SEC,
					     ddata->clk_rate_hz);

	return 0;

Annotation

Implementation Notes