drivers/pwm/pwm-clk.c
Source file repositories/reference/linux-study-clean/drivers/pwm/pwm-clk.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pwm/pwm-clk.c- Extension
.c- Size
- 3622 bytes
- Lines
- 141
- Domain
- Driver Families
- Bucket
- drivers/pwm
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/math64.hlinux/err.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/clk.hlinux/pwm.h
Detected Declarations
struct pwm_clk_chipfunction pwm_clk_applyfunction pwm_clk_probefunction pwm_clk_remove
Annotated Snippet
struct pwm_clk_chip {
struct clk *clk;
bool clk_enabled;
};
static inline struct pwm_clk_chip *to_pwm_clk_chip(struct pwm_chip *chip)
{
return pwmchip_get_drvdata(chip);
}
static int pwm_clk_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
{
struct pwm_clk_chip *pcchip = to_pwm_clk_chip(chip);
int ret;
u32 rate;
u64 period = state->period;
u64 duty_cycle = state->duty_cycle;
if (!state->enabled) {
if (pwm->state.enabled) {
clk_disable(pcchip->clk);
pcchip->clk_enabled = false;
}
return 0;
} else if (!pwm->state.enabled) {
ret = clk_enable(pcchip->clk);
if (ret)
return ret;
pcchip->clk_enabled = true;
}
/*
* We have to enable the clk before setting the rate and duty_cycle,
* that however results in a window where the clk is on with a
* (potentially) different setting. Also setting period and duty_cycle
* are two separate calls, so that probably isn't atomic either.
*/
rate = DIV64_U64_ROUND_UP(NSEC_PER_SEC, period);
ret = clk_set_rate(pcchip->clk, rate);
if (ret)
return ret;
if (state->polarity == PWM_POLARITY_INVERSED)
duty_cycle = period - duty_cycle;
return clk_set_duty_cycle(pcchip->clk, duty_cycle, period);
}
static const struct pwm_ops pwm_clk_ops = {
.apply = pwm_clk_apply,
};
static int pwm_clk_probe(struct platform_device *pdev)
{
struct pwm_chip *chip;
struct pwm_clk_chip *pcchip;
int ret;
chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*pcchip));
if (IS_ERR(chip))
return PTR_ERR(chip);
pcchip = to_pwm_clk_chip(chip);
pcchip->clk = devm_clk_get_prepared(&pdev->dev, NULL);
if (IS_ERR(pcchip->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(pcchip->clk),
"Failed to get clock\n");
chip->ops = &pwm_clk_ops;
ret = pwmchip_add(chip);
if (ret < 0)
return dev_err_probe(&pdev->dev, ret, "Failed to add pwm chip\n");
platform_set_drvdata(pdev, chip);
return 0;
}
static void pwm_clk_remove(struct platform_device *pdev)
{
struct pwm_chip *chip = platform_get_drvdata(pdev);
struct pwm_clk_chip *pcchip = to_pwm_clk_chip(chip);
pwmchip_remove(chip);
if (pcchip->clk_enabled)
clk_disable(pcchip->clk);
}
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/math64.h`, `linux/err.h`, `linux/module.h`, `linux/of.h`, `linux/platform_device.h`, `linux/clk.h`, `linux/pwm.h`.
- Detected declarations: `struct pwm_clk_chip`, `function pwm_clk_apply`, `function pwm_clk_probe`, `function pwm_clk_remove`.
- Atlas domain: Driver Families / drivers/pwm.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.