drivers/pwm/pwm-iqs620a.c

Source file repositories/reference/linux-study-clean/drivers/pwm/pwm-iqs620a.c

File Facts

System
Linux kernel
Corpus path
drivers/pwm/pwm-iqs620a.c
Extension
.c
Size
6629 bytes
Lines
253
Domain
Driver Families
Bucket
drivers/pwm
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct iqs620_pwm_private {
	struct iqs62x_core *iqs62x;
	struct device *dev;
	struct notifier_block notifier;
	struct mutex lock;
	unsigned int duty_scale;
};

static inline struct iqs620_pwm_private *iqs620_pwm_from_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static int iqs620_pwm_init(struct iqs620_pwm_private *iqs620_pwm,
			   unsigned int duty_scale)
{
	struct iqs62x_core *iqs62x = iqs620_pwm->iqs62x;
	int ret;

	if (!duty_scale)
		return regmap_clear_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,
					 IQS620_PWR_SETTINGS_PWM_OUT);

	ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
			   duty_scale - 1);
	if (ret)
		return ret;

	return regmap_set_bits(iqs62x->regmap, IQS620_PWR_SETTINGS,
			       IQS620_PWR_SETTINGS_PWM_OUT);
}

static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			    const struct pwm_state *state)
{
	struct iqs620_pwm_private *iqs620_pwm;
	unsigned int duty_cycle;
	unsigned int duty_scale;
	int ret;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (state->period < IQS620_PWM_PERIOD_NS)
		return -EINVAL;

	iqs620_pwm = iqs620_pwm_from_chip(chip);

	/*
	 * The duty cycle generated by the device is calculated as follows:
	 *
	 * duty_cycle = (IQS620_PWM_DUTY_CYCLE + 1) / 256 * 1 ms
	 *
	 * ...where IQS620_PWM_DUTY_CYCLE is a register value between 0 and 255
	 * (inclusive). Therefore the lowest duty cycle the device can generate
	 * while the output is enabled is 1 / 256 ms.
	 *
	 * For lower duty cycles (e.g. 0), the PWM output is simply disabled to
	 * allow an external pull-down resistor to hold the GPIO3/LTX pin low.
	 */
	duty_cycle = min_t(u64, state->duty_cycle, IQS620_PWM_PERIOD_NS);
	duty_scale = duty_cycle * 256 / IQS620_PWM_PERIOD_NS;

	if (!state->enabled)
		duty_scale = 0;

	mutex_lock(&iqs620_pwm->lock);

	ret = iqs620_pwm_init(iqs620_pwm, duty_scale);
	if (!ret)
		iqs620_pwm->duty_scale = duty_scale;

	mutex_unlock(&iqs620_pwm->lock);

	return ret;
}

static int iqs620_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				struct pwm_state *state)
{
	struct iqs620_pwm_private *iqs620_pwm;

	iqs620_pwm = iqs620_pwm_from_chip(chip);

	mutex_lock(&iqs620_pwm->lock);

	/*
	 * Since the device cannot generate a 0% duty cycle, requests to do so
	 * cause subsequent calls to iqs620_pwm_get_state to report the output
	 * as disabled. This is not ideal, but is the best compromise based on

Annotation

Implementation Notes