drivers/pwm/pwm-mc33xs2410.c

Source file repositories/reference/linux-study-clean/drivers/pwm/pwm-mc33xs2410.c

File Facts

System
Linux kernel
Corpus path
drivers/pwm/pwm-mc33xs2410.c
Extension
.c
Size
11323 bytes
Lines
408
Domain
Driver Families
Bucket
drivers/pwm
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2024 Liebherr-Electronics and Drives GmbH
 *
 * Reference Manual : https://www.nxp.com/docs/en/data-sheet/MC33XS2410.pdf
 *
 * Limitations:
 * - Supports frequencies between 0.5Hz and 2048Hz with following steps:
 *   - 0.5 Hz steps from 0.5 Hz to 32 Hz
 *   - 2 Hz steps from 2 Hz to 128 Hz
 *   - 8 Hz steps from 8 Hz to 512 Hz
 *   - 32 Hz steps from 32 Hz to 2048 Hz
 * - Cannot generate a 0 % duty cycle.
 * - Always produces low output if disabled.
 * - Configuration isn't atomic. When changing polarity, duty cycle or period
 *   the data is taken immediately, counters not being affected, resulting in a
 *   behavior of the output pin that is neither the old nor the new state,
 *   rather something in between.
 */
#define DEFAULT_SYMBOL_NAMESPACE		"PWM_MC33XS2410"

#include <linux/auxiliary_bus.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/math64.h>
#include <linux/mc33xs2410.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pwm.h>

#include <linux/spi/spi.h>

#define MC33XS2410_GLB_CTRL			0x00
#define MC33XS2410_GLB_CTRL_MODE		GENMASK(7, 6)
#define MC33XS2410_GLB_CTRL_MODE_NORMAL		FIELD_PREP(MC33XS2410_GLB_CTRL_MODE, 1)

#define MC33XS2410_PWM_CTRL1			0x05
/* chan in { 1 ... 4 } */
#define MC33XS2410_PWM_CTRL1_POL_INV(chan)	BIT((chan) + 1)

#define MC33XS2410_PWM_CTRL3			0x07
/* chan in { 1 ... 4 } */
#define MC33XS2410_PWM_CTRL3_EN(chan)		BIT(4 + (chan) - 1)

/* chan in { 1 ... 4 } */
#define MC33XS2410_PWM_FREQ(chan)		(0x08 + (chan) - 1)
#define MC33XS2410_PWM_FREQ_STEP		GENMASK(7, 6)
#define MC33XS2410_PWM_FREQ_COUNT		GENMASK(5, 0)

/* chan in { 1 ... 4 } */
#define MC33XS2410_PWM_DC(chan)			(0x0c + (chan) - 1)

#define MC33XS2410_WDT				0x14

#define MC33XS2410_PWM_MIN_PERIOD		488282
/* step in { 0 ... 3 } */
#define MC33XS2410_PWM_MAX_PERIOD(step)		(2000000000 >> (2 * (step)))

#define MC33XS2410_FRAME_IN_ADDR		GENMASK(15, 8)
#define MC33XS2410_FRAME_IN_DATA		GENMASK(7, 0)
#define MC33XS2410_FRAME_IN_ADDR_WR		BIT(7)
#define MC33XS2410_FRAME_IN_DATA_RD		BIT(7)
#define MC33XS2410_FRAME_OUT_DATA		GENMASK(13, 0)

#define MC33XS2410_MAX_TRANSFERS		5

static int mc33xs2410_write_regs(struct spi_device *spi, u8 *reg, u8 *val,
				 unsigned int len)
{
	u16 tx[MC33XS2410_MAX_TRANSFERS];
	int i;

	if (len > MC33XS2410_MAX_TRANSFERS)
		return -EINVAL;

	for (i = 0; i < len; i++)
		tx[i] = FIELD_PREP(MC33XS2410_FRAME_IN_DATA, val[i]) |
			FIELD_PREP(MC33XS2410_FRAME_IN_ADDR,
				   MC33XS2410_FRAME_IN_ADDR_WR | reg[i]);

	return spi_write(spi, tx, len * 2);
}

static int mc33xs2410_read_regs(struct spi_device *spi, u8 *reg, u8 flag,
				u16 *val, unsigned int len)
{
	u16 tx[MC33XS2410_MAX_TRANSFERS];
	u16 rx[MC33XS2410_MAX_TRANSFERS];

Annotation

Implementation Notes