drivers/ras/amd/atl/dehash.c

Source file repositories/reference/linux-study-clean/drivers/ras/amd/atl/dehash.c

File Facts

System
Linux kernel
Corpus path
drivers/ras/amd/atl/dehash.c
Extension
.c
Size
14028 bytes
Lines
458
Domain
Driver Families
Bucket
drivers/ras
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (i <= 2) {
			test_bit    = BIT_ULL(12 + i) & ctx->ret_addr;
			hashed_bit ^= test_bit & hash_ctl_4k;
		}

		/* Use temporary 'test_bit' value to avoid Sparse warnings. */
		test_bit    = BIT_ULL(15 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_64k;
		test_bit    = BIT_ULL(22 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_2M;
		test_bit    = BIT_ULL(29 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_1G;
		test_bit    = BIT_ULL(36 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_1T;
		test_bit    = BIT_ULL(43 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_1T;

		if (hashed_bit != intlv_bit)
			ctx->ret_addr ^= BIT_ULL(base_bit);
	}

	/* Die bits */
	num_intlv_bits = ilog2(ctx->map.num_intlv_dies);

	for (i = 0; i < num_intlv_bits; i++) {
		base_bit = 12 + i;

		intlv_bit = BIT_ULL(base_bit) & ctx->ret_addr;

		hashed_bit = intlv_bit;

		test_bit    = BIT_ULL(20 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_64k;
		test_bit    = BIT_ULL(27 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_2M;
		test_bit    = BIT_ULL(34 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_1G;
		test_bit    = BIT_ULL(41 + i) & ctx->ret_addr;
		hashed_bit ^= test_bit & hash_ctl_1T;

		if (hashed_bit != intlv_bit)
			ctx->ret_addr ^= BIT_ULL(base_bit);
	}

	return 0;
}

int dehash_address(struct addr_ctx *ctx)
{
	switch (ctx->map.intlv_mode) {
	/* No hashing cases. */
	case NONE:
	case NOHASH_2CHAN:
	case NOHASH_4CHAN:
	case NOHASH_8CHAN:
	case NOHASH_16CHAN:
	case NOHASH_32CHAN:
	/* Hashing bits handled earlier during CS ID calculation. */
	case DF4_NPS4_3CHAN_HASH:
	case DF4_NPS2_5CHAN_HASH:
	case DF4_NPS2_6CHAN_HASH:
	case DF4_NPS1_10CHAN_HASH:
	case DF4_NPS1_12CHAN_HASH:
	case DF4p5_NPS2_6CHAN_1K_HASH:
	case DF4p5_NPS2_6CHAN_2K_HASH:
	case DF4p5_NPS1_10CHAN_1K_HASH:
	case DF4p5_NPS1_10CHAN_2K_HASH:
	case DF4p5_NPS1_12CHAN_1K_HASH:
	case DF4p5_NPS1_12CHAN_2K_HASH:
	case DF4p5_NPS0_24CHAN_1K_HASH:
	case DF4p5_NPS0_24CHAN_2K_HASH:
	/* No hash physical address bits, so nothing to do. */
	case DF4p5_NPS4_3CHAN_1K_HASH:
	case DF4p5_NPS4_3CHAN_2K_HASH:
	case DF4p5_NPS2_5CHAN_1K_HASH:
	case DF4p5_NPS2_5CHAN_2K_HASH:
		return 0;

	case DF2_2CHAN_HASH:
		return df2_dehash_addr(ctx);

	case DF3_COD4_2CHAN_HASH:
	case DF3_COD2_4CHAN_HASH:
	case DF3_COD1_8CHAN_HASH:
		return df3_dehash_addr(ctx);

	case DF3_6CHAN:
		return df3_6chan_dehash_addr(ctx);

	case DF4_NPS4_2CHAN_HASH:

Annotation

Implementation Notes