drivers/ras/amd/atl/umc.c

Source file repositories/reference/linux-study-clean/drivers/ras/amd/atl/umc.c

File Facts

System
Linux kernel
Corpus path
drivers/ras/amd/atl/umc.c
Extension
.c
Size
11873 bytes
Lines
419
Domain
Driver Families
Bucket
drivers/ras
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct xor_bits {
	bool	xor_enable;
	u16	col_xor;
	u32	row_xor;
};

#define NUM_BANK_BITS	4
#define NUM_COL_BITS	5
#define NUM_SID_BITS	2

static struct {
	/* UMC::CH::AddrHashBank */
	struct xor_bits	bank[NUM_BANK_BITS];

	/* UMC::CH::AddrHashPC */
	struct xor_bits	pc;

	/* UMC::CH::AddrHashPC2 */
	u8		bank_xor;
} addr_hash;

static struct {
	u8 bank[NUM_BANK_BITS];
	u8 col[NUM_COL_BITS];
	u8 sid[NUM_SID_BITS];
	u8 num_row_lo;
	u8 num_row_hi;
	u8 row_lo;
	u8 row_hi;
	u8 pc;
} bit_shifts;

#define MI300_UMC_CH_BASE	0x90000
#define MI300_ADDR_CFG		(MI300_UMC_CH_BASE + 0x30)
#define MI300_ADDR_SEL		(MI300_UMC_CH_BASE + 0x40)
#define MI300_COL_SEL_LO	(MI300_UMC_CH_BASE + 0x50)
#define MI300_ADDR_SEL_2	(MI300_UMC_CH_BASE + 0xA4)
#define MI300_ADDR_HASH_BANK0	(MI300_UMC_CH_BASE + 0xC8)
#define MI300_ADDR_HASH_PC	(MI300_UMC_CH_BASE + 0xE0)
#define MI300_ADDR_HASH_PC2	(MI300_UMC_CH_BASE + 0xE4)

#define ADDR_HASH_XOR_EN	BIT(0)
#define ADDR_HASH_COL_XOR	GENMASK(13, 1)
#define ADDR_HASH_ROW_XOR	GENMASK(31, 14)
#define ADDR_HASH_BANK_XOR	GENMASK(5, 0)

#define ADDR_CFG_NUM_ROW_LO	GENMASK(11, 8)
#define ADDR_CFG_NUM_ROW_HI	GENMASK(15, 12)

#define ADDR_SEL_BANK0		GENMASK(3, 0)
#define ADDR_SEL_BANK1		GENMASK(7, 4)
#define ADDR_SEL_BANK2		GENMASK(11, 8)
#define ADDR_SEL_BANK3		GENMASK(15, 12)
#define ADDR_SEL_BANK4		GENMASK(20, 16)
#define ADDR_SEL_ROW_LO		GENMASK(27, 24)
#define ADDR_SEL_ROW_HI		GENMASK(31, 28)

#define COL_SEL_LO_COL0		GENMASK(3, 0)
#define COL_SEL_LO_COL1		GENMASK(7, 4)
#define COL_SEL_LO_COL2		GENMASK(11, 8)
#define COL_SEL_LO_COL3		GENMASK(15, 12)
#define COL_SEL_LO_COL4		GENMASK(19, 16)

#define ADDR_SEL_2_BANK5	GENMASK(4, 0)
#define ADDR_SEL_2_CHAN		GENMASK(15, 12)

/*
 * Read UMC::CH::AddrHash{Bank,PC,PC2} registers to get XOR bits used
 * for hashing.
 *
 * Also, read UMC::CH::Addr{Cfg,Sel,Sel2} and UMC::CH:ColSelLo registers to
 * get the values needed to reconstruct the normalized address. Apply additional
 * offsets to the raw register values, as needed.
 *
 * Do this during module init, since the values will not change during run time.
 *
 * These registers are instantiated for each UMC across each AMD Node.
 * However, they should be identically programmed due to the fixed hardware
 * design of MI300 systems. So read the values from Node 0 UMC 0 and keep a
 * single global structure for simplicity.
 */
int get_umc_info_mi300(void)
{
	u32 temp;
	int ret;
	u8 i;

	for (i = 0; i < NUM_BANK_BITS; i++) {
		ret = amd_smn_read(0, MI300_ADDR_HASH_BANK0 + (i * 4), &temp);
		if (ret)

Annotation

Implementation Notes