drivers/reset/reset-aspeed.c

Source file repositories/reference/linux-study-clean/drivers/reset/reset-aspeed.c

File Facts

System: Linux kernel
Corpus path: drivers/reset/reset-aspeed.c
Extension: .c
Size: 10530 bytes
Lines: 254
Domain: Driver Families
Bucket: drivers/reset
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/auxiliary_bus.h
linux/cleanup.h
linux/device.h
linux/io.h
linux/module.h
linux/reset-controller.h
linux/slab.h
dt-bindings/reset/aspeed,ast2700-scu.h

Detected Declarations

struct ast2700_reset_signal
struct aspeed_reset_info
struct aspeed_reset
function aspeed_reset_assert
function aspeed_reset_deassert
function aspeed_reset_status
function aspeed_reset_probe

Annotated Snippet

struct ast2700_reset_signal {
	bool dedicated_clr; /* dedicated reset clr offset */
	u32 offset, bit;
};

struct aspeed_reset_info {
	unsigned int nr_resets;
	const struct ast2700_reset_signal *signal;
};

struct aspeed_reset {
	struct reset_controller_dev rcdev;
	struct aspeed_reset_info *info;
	spinlock_t lock; /* Protect read-modify-write cycle */
	void __iomem *base;
};

static const struct ast2700_reset_signal ast2700_reset0_signals[] = {
	[SCU0_RESET_SDRAM] = { true, SCU0_RESET_CTRL1, BIT(0) },
	[SCU0_RESET_DDRPHY] = { true, SCU0_RESET_CTRL1, BIT(1) },
	[SCU0_RESET_RSA] = { true, SCU0_RESET_CTRL1, BIT(2) },
	[SCU0_RESET_SHA3] = { true, SCU0_RESET_CTRL1, BIT(3) },
	[SCU0_RESET_HACE] = { true, SCU0_RESET_CTRL1, BIT(4) },
	[SCU0_RESET_SOC] = { true, SCU0_RESET_CTRL1, BIT(5) },
	[SCU0_RESET_VIDEO] = { true, SCU0_RESET_CTRL1, BIT(6) },
	[SCU0_RESET_2D] = { true, SCU0_RESET_CTRL1, BIT(7) },
	[SCU0_RESET_PCIS] = { true, SCU0_RESET_CTRL1, BIT(8) },
	[SCU0_RESET_RVAS0] = { true, SCU0_RESET_CTRL1, BIT(9) },
	[SCU0_RESET_RVAS1] = { true, SCU0_RESET_CTRL1, BIT(10) },
	[SCU0_RESET_SM3] = { true, SCU0_RESET_CTRL1, BIT(11) },
	[SCU0_RESET_SM4] = { true, SCU0_RESET_CTRL1, BIT(12) },
	[SCU0_RESET_CRT0] = { true, SCU0_RESET_CTRL1, BIT(13) },
	[SCU0_RESET_ECC] = { true, SCU0_RESET_CTRL1, BIT(14) },
	[SCU0_RESET_DP_PCI] = { true, SCU0_RESET_CTRL1, BIT(15) },
	[SCU0_RESET_UFS] = { true, SCU0_RESET_CTRL1, BIT(16) },
	[SCU0_RESET_EMMC] = { true, SCU0_RESET_CTRL1, BIT(17) },
	[SCU0_RESET_PCIE1RST] = { true, SCU0_RESET_CTRL1, BIT(18) },
	[SCU0_RESET_PCIE1RSTOE] = { true, SCU0_RESET_CTRL1, BIT(19) },
	[SCU0_RESET_PCIE0RST] = { true, SCU0_RESET_CTRL1, BIT(20) },
	[SCU0_RESET_PCIE0RSTOE] = { true, SCU0_RESET_CTRL1, BIT(21) },
	[SCU0_RESET_JTAG] = { true, SCU0_RESET_CTRL1, BIT(22) },
	[SCU0_RESET_MCTP0] = { true, SCU0_RESET_CTRL1, BIT(23) },
	[SCU0_RESET_MCTP1] = { true, SCU0_RESET_CTRL1, BIT(24) },
	[SCU0_RESET_XDMA0] = { true, SCU0_RESET_CTRL1, BIT(25) },
	[SCU0_RESET_XDMA1] = { true, SCU0_RESET_CTRL1, BIT(26) },
	[SCU0_RESET_H2X1] = { true, SCU0_RESET_CTRL1, BIT(27) },
	[SCU0_RESET_DP] = { true, SCU0_RESET_CTRL1, BIT(28) },
	[SCU0_RESET_DP_MCU] = { true, SCU0_RESET_CTRL1, BIT(29) },
	[SCU0_RESET_SSP] = { true, SCU0_RESET_CTRL1, BIT(30) },
	[SCU0_RESET_H2X0] = { true, SCU0_RESET_CTRL1, BIT(31) },
	[SCU0_RESET_PORTA_VHUB] = { true, SCU0_RESET_CTRL2, BIT(0) },
	[SCU0_RESET_PORTA_PHY3] = { true, SCU0_RESET_CTRL2, BIT(1) },
	[SCU0_RESET_PORTA_XHCI] = { true, SCU0_RESET_CTRL2, BIT(2) },
	[SCU0_RESET_PORTB_VHUB] = { true, SCU0_RESET_CTRL2, BIT(3) },
	[SCU0_RESET_PORTB_PHY3] = { true, SCU0_RESET_CTRL2, BIT(4) },
	[SCU0_RESET_PORTB_XHCI] = { true, SCU0_RESET_CTRL2, BIT(5) },
	[SCU0_RESET_PORTA_VHUB_EHCI] = { true, SCU0_RESET_CTRL2, BIT(6) },
	[SCU0_RESET_PORTB_VHUB_EHCI] = { true, SCU0_RESET_CTRL2, BIT(7) },
	[SCU0_RESET_UHCI] = { true, SCU0_RESET_CTRL2, BIT(8) },
	[SCU0_RESET_TSP] = { true, SCU0_RESET_CTRL2, BIT(9) },
	[SCU0_RESET_E2M0] = { true, SCU0_RESET_CTRL2, BIT(10) },
	[SCU0_RESET_E2M1] = { true, SCU0_RESET_CTRL2, BIT(11) },
	[SCU0_RESET_VLINK] = { true, SCU0_RESET_CTRL2, BIT(12) },
};

static const struct ast2700_reset_signal ast2700_reset1_signals[] = {
	[SCU1_RESET_LPC0] = { true, SCU1_RESET_CTRL1, BIT(0) },
	[SCU1_RESET_LPC1] = { true, SCU1_RESET_CTRL1, BIT(1) },
	[SCU1_RESET_MII] = { true, SCU1_RESET_CTRL1, BIT(2) },
	[SCU1_RESET_PECI] = { true, SCU1_RESET_CTRL1, BIT(3) },
	[SCU1_RESET_PWM] = { true, SCU1_RESET_CTRL1, BIT(4) },
	[SCU1_RESET_MAC0] = { true, SCU1_RESET_CTRL1, BIT(5) },
	[SCU1_RESET_MAC1] = { true, SCU1_RESET_CTRL1, BIT(6) },
	[SCU1_RESET_MAC2] = { true, SCU1_RESET_CTRL1, BIT(7) },
	[SCU1_RESET_ADC] = { true, SCU1_RESET_CTRL1, BIT(8) },
	[SCU1_RESET_SD] = { true, SCU1_RESET_CTRL1, BIT(9) },
	[SCU1_RESET_ESPI0] = { true, SCU1_RESET_CTRL1, BIT(10) },
	[SCU1_RESET_ESPI1] = { true, SCU1_RESET_CTRL1, BIT(11) },
	[SCU1_RESET_JTAG1] = { true, SCU1_RESET_CTRL1, BIT(12) },
	[SCU1_RESET_SPI0] = { true, SCU1_RESET_CTRL1, BIT(13) },
	[SCU1_RESET_SPI1] = { true, SCU1_RESET_CTRL1, BIT(14) },
	[SCU1_RESET_SPI2] = { true, SCU1_RESET_CTRL1, BIT(15) },
	[SCU1_RESET_I3C0] = { true, SCU1_RESET_CTRL1, BIT(16) },
	[SCU1_RESET_I3C1] = { true, SCU1_RESET_CTRL1, BIT(17) },
	[SCU1_RESET_I3C2] = { true, SCU1_RESET_CTRL1, BIT(18) },
	[SCU1_RESET_I3C3] = { true, SCU1_RESET_CTRL1, BIT(19) },
	[SCU1_RESET_I3C4] = { true, SCU1_RESET_CTRL1, BIT(20) },
	[SCU1_RESET_I3C5] = { true, SCU1_RESET_CTRL1, BIT(21) },
	[SCU1_RESET_I3C6] = { true, SCU1_RESET_CTRL1, BIT(22) },
	[SCU1_RESET_I3C7] = { true, SCU1_RESET_CTRL1, BIT(23) },

Annotation

Immediate include surface: `linux/auxiliary_bus.h`, `linux/cleanup.h`, `linux/device.h`, `linux/io.h`, `linux/module.h`, `linux/reset-controller.h`, `linux/slab.h`, `dt-bindings/reset/aspeed,ast2700-scu.h`.
Detected declarations: `struct ast2700_reset_signal`, `struct aspeed_reset_info`, `struct aspeed_reset`, `function aspeed_reset_assert`, `function aspeed_reset_deassert`, `function aspeed_reset_status`, `function aspeed_reset_probe`.
Atlas domain: Driver Families / drivers/reset.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.