drivers/reset/reset-eic7700.c
Source file repositories/reference/linux-study-clean/drivers/reset/reset-eic7700.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/reset/reset-eic7700.c- Extension
.c- Size
- 16900 bytes
- Lines
- 430
- Domain
- Driver Families
- Bucket
- drivers/reset
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/err.hlinux/init.hlinux/of.hlinux/platform_device.hlinux/regmap.hlinux/reset-controller.hlinux/slab.hlinux/types.hdt-bindings/reset/eswin,eic7700-reset.h
Detected Declarations
struct eic7700_reset_datastruct eic7700_regfunction to_eic7700_reset_datafunction eic7700_reset_assertfunction eic7700_reset_deassertfunction eic7700_reset_resetfunction eic7700_reset_probe
Annotated Snippet
struct eic7700_reset_data {
struct reset_controller_dev rcdev;
struct regmap *regmap;
};
static const struct regmap_config eic7700_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = 0x1fc,
};
struct eic7700_reg {
u32 reg;
u32 bit;
};
static inline struct eic7700_reset_data *
to_eic7700_reset_data(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct eic7700_reset_data, rcdev);
}
#define EIC7700_RESET(id, reg, bit)[id] = \
{ SYSCRG_RESET_OFFSET + (reg) * sizeof(u32), BIT(bit) }
/* mapping table for reset ID to register offset and reset bit */
static const struct eic7700_reg eic7700_reset[] = {
EIC7700_RESET(EIC7700_RESET_NOC_NSP, 0, 0),
EIC7700_RESET(EIC7700_RESET_NOC_CFG, 0, 1),
EIC7700_RESET(EIC7700_RESET_RNOC_NSP, 0, 2),
EIC7700_RESET(EIC7700_RESET_SNOC_TCU, 0, 3),
EIC7700_RESET(EIC7700_RESET_SNOC_U84, 0, 4),
EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_XSR, 0, 5),
EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_XMR, 0, 6),
EIC7700_RESET(EIC7700_RESET_SNOC_PCIE_PR, 0, 7),
EIC7700_RESET(EIC7700_RESET_SNOC_NPU, 0, 8),
EIC7700_RESET(EIC7700_RESET_SNOC_JTAG, 0, 9),
EIC7700_RESET(EIC7700_RESET_SNOC_DSP, 0, 10),
EIC7700_RESET(EIC7700_RESET_SNOC_DDRC1_P2, 0, 11),
EIC7700_RESET(EIC7700_RESET_SNOC_DDRC1_P1, 0, 12),
EIC7700_RESET(EIC7700_RESET_SNOC_DDRC0_P2, 0, 13),
EIC7700_RESET(EIC7700_RESET_SNOC_DDRC0_P1, 0, 14),
EIC7700_RESET(EIC7700_RESET_SNOC_D2D, 0, 15),
EIC7700_RESET(EIC7700_RESET_SNOC_AON, 0, 16),
EIC7700_RESET(EIC7700_RESET_GPU_AXI, 1, 0),
EIC7700_RESET(EIC7700_RESET_GPU_CFG, 1, 1),
EIC7700_RESET(EIC7700_RESET_GPU_GRAY, 1, 2),
EIC7700_RESET(EIC7700_RESET_GPU_JONES, 1, 3),
EIC7700_RESET(EIC7700_RESET_GPU_SPU, 1, 4),
EIC7700_RESET(EIC7700_RESET_DSP_AXI, 2, 0),
EIC7700_RESET(EIC7700_RESET_DSP_CFG, 2, 1),
EIC7700_RESET(EIC7700_RESET_DSP_DIV4, 2, 2),
EIC7700_RESET(EIC7700_RESET_DSP_DIV0, 2, 4),
EIC7700_RESET(EIC7700_RESET_DSP_DIV1, 2, 5),
EIC7700_RESET(EIC7700_RESET_DSP_DIV2, 2, 6),
EIC7700_RESET(EIC7700_RESET_DSP_DIV3, 2, 7),
EIC7700_RESET(EIC7700_RESET_D2D_AXI, 3, 0),
EIC7700_RESET(EIC7700_RESET_D2D_CFG, 3, 1),
EIC7700_RESET(EIC7700_RESET_D2D_PRST, 3, 2),
EIC7700_RESET(EIC7700_RESET_D2D_RAW_PCS, 3, 4),
EIC7700_RESET(EIC7700_RESET_D2D_RX, 3, 5),
EIC7700_RESET(EIC7700_RESET_D2D_TX, 3, 6),
EIC7700_RESET(EIC7700_RESET_D2D_CORE, 3, 7),
EIC7700_RESET(EIC7700_RESET_DDR1_ARST, 4, 0),
EIC7700_RESET(EIC7700_RESET_DDR1_TRACE, 4, 6),
EIC7700_RESET(EIC7700_RESET_DDR0_ARST, 4, 16),
EIC7700_RESET(EIC7700_RESET_DDR_CFG, 4, 21),
EIC7700_RESET(EIC7700_RESET_DDR0_TRACE, 4, 22),
EIC7700_RESET(EIC7700_RESET_DDR_CORE, 4, 23),
EIC7700_RESET(EIC7700_RESET_DDR_PRST, 4, 26),
EIC7700_RESET(EIC7700_RESET_TCU_AXI, 5, 0),
EIC7700_RESET(EIC7700_RESET_TCU_CFG, 5, 1),
EIC7700_RESET(EIC7700_RESET_TCU_TBU0, 5, 4),
EIC7700_RESET(EIC7700_RESET_TCU_TBU1, 5, 5),
EIC7700_RESET(EIC7700_RESET_TCU_TBU2, 5, 6),
EIC7700_RESET(EIC7700_RESET_TCU_TBU3, 5, 7),
EIC7700_RESET(EIC7700_RESET_TCU_TBU4, 5, 8),
EIC7700_RESET(EIC7700_RESET_TCU_TBU5, 5, 9),
EIC7700_RESET(EIC7700_RESET_TCU_TBU6, 5, 10),
EIC7700_RESET(EIC7700_RESET_TCU_TBU7, 5, 11),
EIC7700_RESET(EIC7700_RESET_TCU_TBU8, 5, 12),
EIC7700_RESET(EIC7700_RESET_TCU_TBU9, 5, 13),
EIC7700_RESET(EIC7700_RESET_TCU_TBU10, 5, 14),
EIC7700_RESET(EIC7700_RESET_TCU_TBU11, 5, 15),
EIC7700_RESET(EIC7700_RESET_TCU_TBU12, 5, 16),
EIC7700_RESET(EIC7700_RESET_TCU_TBU13, 5, 17),
EIC7700_RESET(EIC7700_RESET_TCU_TBU14, 5, 18),
EIC7700_RESET(EIC7700_RESET_TCU_TBU15, 5, 19),
EIC7700_RESET(EIC7700_RESET_TCU_TBU16, 5, 20),Annotation
- Immediate include surface: `linux/err.h`, `linux/init.h`, `linux/of.h`, `linux/platform_device.h`, `linux/regmap.h`, `linux/reset-controller.h`, `linux/slab.h`, `linux/types.h`.
- Detected declarations: `struct eic7700_reset_data`, `struct eic7700_reg`, `function to_eic7700_reset_data`, `function eic7700_reset_assert`, `function eic7700_reset_deassert`, `function eic7700_reset_reset`, `function eic7700_reset_probe`.
- Atlas domain: Driver Families / drivers/reset.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.