drivers/reset/reset-ma35d1.c

Source file repositories/reference/linux-study-clean/drivers/reset/reset-ma35d1.c

File Facts

System: Linux kernel
Corpus path: drivers/reset/reset-ma35d1.c
Extension: .c
Size: 7276 bytes
Lines: 233
Domain: Driver Families
Bucket: drivers/reset
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/bits.h
linux/container_of.h
linux/device.h
linux/err.h
linux/io.h
linux/kernel.h
linux/of.h
linux/platform_device.h
linux/reboot.h
linux/reset-controller.h
linux/spinlock.h
dt-bindings/reset/nuvoton,ma35d1-reset.h

Detected Declarations

struct ma35d1_reset_data
function ma35d1_restart_handler
function ma35d1_reset_update
function ma35d1_reset_assert
function ma35d1_reset_deassert
function ma35d1_reset_status
function ma35d1_reset_probe

Annotated Snippet

struct ma35d1_reset_data {
	struct reset_controller_dev rcdev;
	void __iomem *base;
	/* protect registers against concurrent read-modify-write */
	spinlock_t lock;
};

static const struct {
	u32 reg_ofs;
	u32 bit;
} ma35d1_reset_map[] = {
	[MA35D1_RESET_CHIP] =    {0x20, 0},
	[MA35D1_RESET_CA35CR0] = {0x20, 1},
	[MA35D1_RESET_CA35CR1] = {0x20, 2},
	[MA35D1_RESET_CM4] =     {0x20, 3},
	[MA35D1_RESET_PDMA0] =   {0x20, 4},
	[MA35D1_RESET_PDMA1] =   {0x20, 5},
	[MA35D1_RESET_PDMA2] =   {0x20, 6},
	[MA35D1_RESET_PDMA3] =   {0x20, 7},
	[MA35D1_RESET_DISP] =    {0x20, 9},
	[MA35D1_RESET_VCAP0] =   {0x20, 10},
	[MA35D1_RESET_VCAP1] =   {0x20, 11},
	[MA35D1_RESET_GFX] =     {0x20, 12},
	[MA35D1_RESET_VDEC] =    {0x20, 13},
	[MA35D1_RESET_WHC0] =    {0x20, 14},
	[MA35D1_RESET_WHC1] =    {0x20, 15},
	[MA35D1_RESET_GMAC0] =   {0x20, 16},
	[MA35D1_RESET_GMAC1] =   {0x20, 17},
	[MA35D1_RESET_HWSEM] =   {0x20, 18},
	[MA35D1_RESET_EBI] =     {0x20, 19},
	[MA35D1_RESET_HSUSBH0] = {0x20, 20},
	[MA35D1_RESET_HSUSBH1] = {0x20, 21},
	[MA35D1_RESET_HSUSBD] =  {0x20, 22},
	[MA35D1_RESET_USBHL] =   {0x20, 23},
	[MA35D1_RESET_SDH0] =    {0x20, 24},
	[MA35D1_RESET_SDH1] =    {0x20, 25},
	[MA35D1_RESET_NAND] =    {0x20, 26},
	[MA35D1_RESET_GPIO] =    {0x20, 27},
	[MA35D1_RESET_MCTLP] =   {0x20, 28},
	[MA35D1_RESET_MCTLC] =   {0x20, 29},
	[MA35D1_RESET_DDRPUB] =  {0x20, 30},
	[MA35D1_RESET_TMR0] =    {0x24, 2},
	[MA35D1_RESET_TMR1] =    {0x24, 3},
	[MA35D1_RESET_TMR2] =    {0x24, 4},
	[MA35D1_RESET_TMR3] =    {0x24, 5},
	[MA35D1_RESET_I2C0] =    {0x24, 8},
	[MA35D1_RESET_I2C1] =    {0x24, 9},
	[MA35D1_RESET_I2C2] =    {0x24, 10},
	[MA35D1_RESET_I2C3] =    {0x24, 11},
	[MA35D1_RESET_QSPI0] =   {0x24, 12},
	[MA35D1_RESET_SPI0] =    {0x24, 13},
	[MA35D1_RESET_SPI1] =    {0x24, 14},
	[MA35D1_RESET_SPI2] =    {0x24, 15},
	[MA35D1_RESET_UART0] =   {0x24, 16},
	[MA35D1_RESET_UART1] =   {0x24, 17},
	[MA35D1_RESET_UART2] =   {0x24, 18},
	[MA35D1_RESET_UART3] =   {0x24, 19},
	[MA35D1_RESET_UART4] =   {0x24, 20},
	[MA35D1_RESET_UART5] =   {0x24, 21},
	[MA35D1_RESET_UART6] =   {0x24, 22},
	[MA35D1_RESET_UART7] =   {0x24, 23},
	[MA35D1_RESET_CANFD0] =  {0x24, 24},
	[MA35D1_RESET_CANFD1] =  {0x24, 25},
	[MA35D1_RESET_EADC0] =   {0x24, 28},
	[MA35D1_RESET_I2S0] =    {0x24, 29},
	[MA35D1_RESET_SC0] =     {0x28, 0},
	[MA35D1_RESET_SC1] =     {0x28, 1},
	[MA35D1_RESET_QSPI1] =   {0x28, 4},
	[MA35D1_RESET_SPI3] =    {0x28, 6},
	[MA35D1_RESET_EPWM0] =   {0x28, 16},
	[MA35D1_RESET_EPWM1] =   {0x28, 17},
	[MA35D1_RESET_QEI0] =    {0x28, 22},
	[MA35D1_RESET_QEI1] =    {0x28, 23},
	[MA35D1_RESET_ECAP0] =   {0x28, 26},
	[MA35D1_RESET_ECAP1] =   {0x28, 27},
	[MA35D1_RESET_CANFD2] =  {0x28, 28},
	[MA35D1_RESET_ADC0] =    {0x28, 31},
	[MA35D1_RESET_TMR4] =    {0x2C, 0},
	[MA35D1_RESET_TMR5] =    {0x2C, 1},
	[MA35D1_RESET_TMR6] =    {0x2C, 2},
	[MA35D1_RESET_TMR7] =    {0x2C, 3},
	[MA35D1_RESET_TMR8] =    {0x2C, 4},
	[MA35D1_RESET_TMR9] =    {0x2C, 5},
	[MA35D1_RESET_TMR10] =   {0x2C, 6},
	[MA35D1_RESET_TMR11] =   {0x2C, 7},
	[MA35D1_RESET_UART8] =   {0x2C, 8},
	[MA35D1_RESET_UART9] =   {0x2C, 9},
	[MA35D1_RESET_UART10] =  {0x2C, 10},
	[MA35D1_RESET_UART11] =  {0x2C, 11},
	[MA35D1_RESET_UART12] =  {0x2C, 12},

Annotation

Immediate include surface: `linux/bits.h`, `linux/container_of.h`, `linux/device.h`, `linux/err.h`, `linux/io.h`, `linux/kernel.h`, `linux/of.h`, `linux/platform_device.h`.
Detected declarations: `struct ma35d1_reset_data`, `function ma35d1_restart_handler`, `function ma35d1_reset_update`, `function ma35d1_reset_assert`, `function ma35d1_reset_deassert`, `function ma35d1_reset_status`, `function ma35d1_reset_probe`.
Atlas domain: Driver Families / drivers/reset.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.