drivers/reset/reset-qcom-pdc.c

Source file repositories/reference/linux-study-clean/drivers/reset/reset-qcom-pdc.c

File Facts

System
Linux kernel
Corpus path
drivers/reset/reset-qcom-pdc.c
Extension
.c
Size
4364 bytes
Lines
162
Domain
Driver Families
Bucket
drivers/reset
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qcom_pdc_reset_map {
	u8 bit;
};

struct qcom_pdc_reset_desc {
	const struct qcom_pdc_reset_map *resets;
	size_t num_resets;
	unsigned int offset;
};

struct qcom_pdc_reset_data {
	struct reset_controller_dev rcdev;
	struct regmap *regmap;
	const struct qcom_pdc_reset_desc *desc;
};

static const struct regmap_config pdc_regmap_config = {
	.name		= "pdc-reset",
	.reg_bits	= 32,
	.reg_stride	= 4,
	.val_bits	= 32,
	.max_register	= 0x20000,
};

static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
	[PDC_APPS_SYNC_RESET] = {0},
	[PDC_SP_SYNC_RESET] = {1},
	[PDC_AUDIO_SYNC_RESET] = {2},
	[PDC_SENSORS_SYNC_RESET] = {3},
	[PDC_AOP_SYNC_RESET] = {4},
	[PDC_DEBUG_SYNC_RESET] = {5},
	[PDC_GPU_SYNC_RESET] = {6},
	[PDC_DISPLAY_SYNC_RESET] = {7},
	[PDC_COMPUTE_SYNC_RESET] = {8},
	[PDC_MODEM_SYNC_RESET] = {9},
};

static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
	.resets = sdm845_pdc_resets,
	.num_resets = ARRAY_SIZE(sdm845_pdc_resets),
	.offset = RPMH_SDM845_PDC_SYNC_RESET,
};

static const struct qcom_pdc_reset_map sc7280_pdc_resets[] = {
	[PDC_APPS_SYNC_RESET] = {0},
	[PDC_SP_SYNC_RESET] = {1},
	[PDC_AUDIO_SYNC_RESET] = {2},
	[PDC_SENSORS_SYNC_RESET] = {3},
	[PDC_AOP_SYNC_RESET] = {4},
	[PDC_DEBUG_SYNC_RESET] = {5},
	[PDC_GPU_SYNC_RESET] = {6},
	[PDC_DISPLAY_SYNC_RESET] = {7},
	[PDC_COMPUTE_SYNC_RESET] = {8},
	[PDC_MODEM_SYNC_RESET] = {9},
	[PDC_WLAN_RF_SYNC_RESET] = {10},
	[PDC_WPSS_SYNC_RESET] = {11},
};

static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
	.resets = sc7280_pdc_resets,
	.num_resets = ARRAY_SIZE(sc7280_pdc_resets),
	.offset = RPMH_SC7280_PDC_SYNC_RESET,
};

static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
				struct reset_controller_dev *rcdev)
{
	return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
}

static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
					unsigned long idx)
{
	struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
	u32 mask = BIT(data->desc->resets[idx].bit);

	return regmap_update_bits(data->regmap, data->desc->offset, mask, mask);
}

static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
					unsigned long idx)
{
	struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
	u32 mask = BIT(data->desc->resets[idx].bit);

	return regmap_update_bits(data->regmap, data->desc->offset, mask, 0);
}

static const struct reset_control_ops qcom_pdc_reset_ops = {
	.assert = qcom_pdc_control_assert,

Annotation

Implementation Notes