drivers/reset/reset-th1520.c

Source file repositories/reference/linux-study-clean/drivers/reset/reset-th1520.c

File Facts

System
Linux kernel
Corpus path
drivers/reset/reset-th1520.c
Extension
.c
Size
23623 bytes
Lines
984
Domain
Driver Families
Bucket
drivers/reset
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct th1520_reset_map {
	u32 bit;
	u32 reg;
};

struct th1520_reset_priv {
	struct reset_controller_dev rcdev;
	struct regmap *map;
	const struct th1520_reset_map *resets;
};

struct th1520_reset_data {
	const struct th1520_reset_map *resets;
	size_t num;
};

static const struct th1520_reset_map th1520_resets[] = {
	[TH1520_RESET_ID_GPU] = {
		.bit = TH1520_GPU_SW_GPU_RST,
		.reg = TH1520_GPU_RST_CFG,
	},
	[TH1520_RESET_ID_GPU_CLKGEN] = {
		.bit = TH1520_GPU_SW_CLKGEN_RST,
		.reg = TH1520_GPU_RST_CFG,
	},
	[TH1520_RESET_ID_DPU_AHB] = {
		.bit = TH1520_DPU_SW_DPU_HRST,
		.reg = TH1520_DPU_RST_CFG,
	},
	[TH1520_RESET_ID_DPU_AXI] = {
		.bit = TH1520_DPU_SW_DPU_ARST,
		.reg = TH1520_DPU_RST_CFG,
	},
	[TH1520_RESET_ID_DPU_CORE] = {
		.bit = TH1520_DPU_SW_DPU_CRST,
		.reg = TH1520_DPU_RST_CFG,
	},
	[TH1520_RESET_ID_DSI0_APB] = {
		.bit = TH1520_DSI_SW_DSI_PRST,
		.reg = TH1520_DSI0_RST_CFG,
	},
	[TH1520_RESET_ID_DSI1_APB] = {
		.bit = TH1520_DSI_SW_DSI_PRST,
		.reg = TH1520_DSI1_RST_CFG,
	},
	[TH1520_RESET_ID_HDMI] = {
		.bit = TH1520_HDMI_SW_MAIN_RST,
		.reg = TH1520_HDMI_RST_CFG,
	},
	[TH1520_RESET_ID_HDMI_APB] = {
		.bit = TH1520_HDMI_SW_PRST,
		.reg = TH1520_HDMI_RST_CFG,
	},
	[TH1520_RESET_ID_VOAXI] = {
		.bit = BIT(0),
		.reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
	},
	[TH1520_RESET_ID_VOAXI_APB] = {
		.bit = BIT(1),
		.reg = TH1520_AXI4_VO_DW_AXI_RST_CFG,
	},
	[TH1520_RESET_ID_X2H_DPU_AXI] = {
		.bit = BIT(0),
		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
	},
	[TH1520_RESET_ID_X2H_DPU_AHB] = {
		.bit = BIT(1),
		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
	},
	[TH1520_RESET_ID_X2H_DPU1_AXI] = {
		.bit = BIT(2),
		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
	},
	[TH1520_RESET_ID_X2H_DPU1_AHB] = {
		.bit = BIT(3),
		.reg = TH1520_X2H_X4_VOSYS_DW_RST_CFG,
	},
};

static const struct th1520_reset_map th1520_ap_resets[] = {
	[TH1520_RESET_ID_BROM] = {
		.bit = BIT(0),
		.reg = TH1520_BROM_RST_CFG,
	},
	[TH1520_RESET_ID_C910_TOP] = {
		.bit = BIT(0),
		.reg = TH1520_C910_RST_CFG,
	},
	[TH1520_RESET_ID_NPU] =  {
		.bit = BIT(0),

Annotation

Implementation Notes